Stencils and problem partitionings: Their influence on the performance of multiple processor systems

Given a discretization stencil, partitioning the problem domain is an important first step for the efficient solution of partial differential equations on multiple processor systems. Partitions are derived that minimize interprocessor communication when the number of processors is known a priori and each domain partition is assigned to a different processor. This partitioning technique uses the stencil structure to select appropriate partition shapes. For square problem domains, it is shown that non-standard partitions (e.g., hexagons) are frequently preferable to the standard square partitions for a variety of commonly used stencils. This investigation is concluded with a formalization of the relationship between partition shape, stencil structure, and architecture, allowing selection of optimal partitions for a variety of parallel systems

Modeling of Topologies of Interconnection Networks based on Multidimensional Multiplicity

Modern SoCs are becoming more complex with the integration of heterogeneous components (IPs). For this purpose, a high performance interconnection medium is required to handle the complexity. Hence NoCs come into play enabling the integration of more IPs into the SoC with increased performance. These NoCs are based on the concept of Interconnection networks used to connect parallel machines. In response to the MARTE RFP of the OMG, a notation of multidimensional multiplicity has been proposed which permits to model repetitive structures and topologies. This report presents a modeling methodology based on this notation that can be used to model a family of Interconnection Networks called Delta Networks which in turn can be used for the construction of NoCs

A Complexity Analysis of Smart Pixel Switching Nodes for Photonic Extended Generalized Shuffle Switching Networks

This paper studies the architectural tradeoffs found in the use of smart pixels for nodes within photonic switching interconnection networks are discussed. The particular networks of interest within the analysis are strictly nonblocking extended generalized shuffle (EGS) networks. Several performance metrics are defined for the analysis, and the effect of node size on these metrics is studied. Optimum node sizes are defined for each of the performance metrics and system-level limitations are identified

Optimizing Data Intensive Flows for Networks on Chips

Data flow analysis and optimization is considered for homogeneous rectangular mesh networks. We propose a flow matrix equation which allows a closed-form characterization of the nature of the minimal time solution, speedup and a simple method to determine when and how much load to distribute to processors. We also propose a rigorous mathematical proof about the flow matrix optimal solution existence and that the solution is unique. The methodology introduced here is applicable to many interconnection networks and switching protocols (as an example we examine toroidal networks and hypercube networks in this paper). An important application is improving chip area and chip scalability for networks on chips processing divisible style loads

Probabilistic structural mechanics research for parallel processing computers

Aerospace structures and spacecraft are a complex assemblage of structural components that are subjected to a variety of complex, cyclic, and transient loading conditions. Significant modeling uncertainties are present in these structures, in addition to the inherent randomness of material properties and loads. To properly account for these uncertainties in evaluating and assessing the reliability of these components and structures, probabilistic structural mechanics (PSM) procedures must be used. Much research has focused on basic theory development and the development of approximate analytic solution methods in random vibrations and structural reliability. Practical application of PSM methods was hampered by their computationally intense nature. Solution of PSM problems requires repeated analyses of structures that are often large, and exhibit nonlinear and/or dynamic response behavior. These methods are all inherently parallel and ideally suited to implementation on parallel processing computers. New hardware architectures and innovative control software and solution methodologies are needed to make solution of large scale PSM problems practical

Impact of 3D IC on NoC Topologies: A Wire Delay Consideration

International audienceIn this paper, we perform an exploration of 3D NoC architectures through physical design implementation based on two tiers Tezzaron 3D technology. The 3D NoC partitioning is done by dividing the NoC's datapath component into two blocks placed in the two tiers. Two Stacked NoC architectures namely Stacked 3D-Mesh NoC and Stacked 2D-Hexagonal NoC developed based on this partitioning strategy are analyzed by comparing their performances with Stacked 2D-Mesh NoC and classical 2D- Mesh and 3D-Mesh NoC. In order to measure the impact of wire delay on performance, two technology libraries (130 nm and 45 nm) representing old and advanced technologies have been used for the performance analysis. Results from physical implementations show that in advanced technologies such as 45 nm and below, the performance of Stacked 2D NoC topologies with datapath partitioning method have better performances compared with traditional 2D/3D Mesh topologies and Stacked 3D Mesh topology. We advocate here that with stacking there is no need for 3D NoC topologies for advanced 2-tier 3D IC and this is also confirmed for multistage networks like butterfly

Microring-Resonator-Based Switch Architectures for Optical Networks

Integrated silicon photonics provides a promising platform for chip-based, high-speed optical signal processing due to its compatibility with complementary metal-oxide semiconductor (CMOS) fabrication processes. They are attracting significant research and development interest globally and making a huge impact on green information and communication technologies, and high-performance computing systems. Microring resonators (MRRs) show the versatility to implement a variety of network functions, compact footprint, and complementary metal-oxide semiconductor compatibility, and demonstrate the viability applied in photonic integrated technologies for both chip level and board-to-board interconnects. Furthermore, MRRs have excellent wavelength selection properties and can be used to design tunable filters, modulators, wavelength converters, and switches that are critical components for optical interconnects. The research work of this dissertation is focused on investigating how to develop MRR-based switches and switch architectures for possible applications not only in optical interconnection networks but also in flexible-grid on-chip networks for optical communication systems. The basic properties and performances of the MRR switches and the MRR switch architectures related to their applications in the networks are examined. In particular, how to design and how to configure high performance, bandwidth variable, low insertion loss, and weak crosstalk MRR-based switches and switch architectures are investigated for applications in optical interconnection networks and in flexible-grid on-chip networks for optical communication systems. The works include several parts as follows. The physical characteristics of microring resonator switching devices are thoroughly analyzed using a model based on the field coupling matrix theory. The spectral response and insertion loss properties of these switching elements are simulated using the developed model. Then we investigate the optimal design of high-order MRR-based switch devices. Spectral shaping of the passbands of microring resonator switches is studied. Multistage high-order microring resonator-based optical switch structures are proposed to achieve steep-edge flat-top spectral passband. Using the transfer matrix analysis model, the spectral response behaviors of the switch structures are simulated. The performances of the proposed multistage high-order microring resonator-based optical switch structures and the high-order microring-resonator-based optical switch structures without stages are studied and compared. Two types of MRR-based switch architectures are proposed to realize variable output bandwidths varying from 0 to 4 THz. One consists of 320, 160, and 80 third-order MRR switches with -3 dB passband widths of 12.5, 25, and 50 GHz, respectively. Another one is two-stage switch structure. In the first stage there are 4 third-order MRR switches with the passband widths of 1 THz. In second stage, there are 80, 40, 20 third-order MRR switches with the passband widths of 12.5, 25, and 50 GHz, respectively. Their insertion losses and crosstalks in the worst cases are numerically analyzed and compared in order to show the feasibility for the architectures to be applied in flexible optical networks. MRR-based bandwidth-variable wavelength selective switch architectures with multiple input and output ports are proposed for flexible optical networks. The light transmission behaviors of a 1 by N MRR-based WSS are analyzed in detail based on numerical simulation using transfer matrix theory. Two types of N by N MRR-based WSS architectures consisting of MRR-based WSSs and MRR-based WSSs, and MRR-based WSSs and optical couplers are proposed. The performances of the proposed architectures are studied. Scalable optical interconnections based on MRRs are proposed, which consist mainly of microring resonator devices: microring lasers, microring switches, microring de-multiplexers, and integrated photo-dectors. Their throughput capacities, end-to-end time latencies, and transmission packet loss rates are evaluated using OMNet++. In summary, the research of the dissertation contributes to develop high performance, variable bandwidth, low insertion loss, and low crosstalk MRR-based optical switches and switch architectures to adapt to dynamic source allocation of flexible-grid optical networks