Beamforming in MISO Systems: Empirical Results and EVM-based Analysis

We present an analytical, simulation, and experimental-based study of beamforming Multiple Input Single Output (MISO) systems. We analyze the performance of beamforming MISO systems taking into account implementation complexity and effects of imperfect channel estimate, delayed feedback, real Radio Frequency (RF) hardware, and imperfect timing synchronization. Our results show that efficient implementation of codebook-based beamforming MISO systems with good performance is feasible in the presence of channel and implementation-induced imperfections. As part of our study we develop a framework for Average Error Vector Magnitude Squared (AEVMS)-based analysis of beamforming MISO systems which facilitates comparison of analytical, simulation, and experimental results on the same scale. In addition, AEVMS allows fair comparison of experimental results obtained from different wireless testbeds. We derive novel expressions for the AEVMS of beamforming MISO systems and show how the AEVMS relates to important system characteristics like the diversity gain, coding gain, and error floor.Comment: Submitted to IEEE Transactions on Wireless Communications, November 200

HDL modeling for analysis and optimization of asynchronous controllers

Journal ArticleWe propose a simulation-based technique for analysis and optimization of extended burst-mode (XBM) asynchronous controllers. In asynchronous controllers of this sort, timing information on control signals is significant both for performance enhancement and timing validation. Timing information, specifically information about relative signal arrival times, helps us improve the controller's response time and to detect delay faults within controllers in the early synthesis stage. If the timing information of the controller's environment is also known, we can use this information to identify fundamental mode violations. Our approach uses stochastic simulation of HDL programs derived from the original XBM specifications to gather information about signal timing and long-term transition probabilities

ToPoliNano: Nanoarchitectures Design Made Real

Many facts about emerging nanotechnologies are yet to be assessed. There are still major concerns, for instance, about maximum achievable device density, or about which architecture is best fit for a specific application. Growing complexity requires taking into account many aspects of technology, application and architecture at the same time. Researchers face problems that are not new per se, but are now subject to very different constraints, that need to be captured by design tools. Among the emerging nanotechnologies, two-dimensional nanowire based arrays represent promising nanostructures, especially for massively parallel computing architectures. Few attempts have been done, aimed at giving the possibility to explore architectural solutions, deriving information from extensive and reliable nanoarray characterization. Moreover, in the nanotechnology arena there is still not a clear winner, so it is important to be able to target different technologies, not to miss the next big thing. We present a tool, ToPoliNano, that enables such a multi-technological characterization in terms of logic behavior, power and timing performance, area and layout constraints, on the basis of specific technological and topological descriptions. This tool can aid the design process, beside providing a comprehensive simulation framework for DC and timing simulations, and detailed power analysis. Design and simulation results will be shown for nanoarray-based circuits. ToPoliNano is the first real design tool that tackles the top down design of a circuit based on emerging technologie

Living in a Simulation? An Empirical Investigation of a Smart Driving-Simulation Testing System

The internet of things (IoT) generally refers to the embedding of computing and communication devices in various types of physical objects (e.g., automobiles) used in people’s daily lives. This paper draws on feedback intervention theory to investigate the impact of IoT-enabled immediate feedback interventions on individual task performance. Our research context is a smart test-simulation service based on internet-of-vehicles (IoV) technology that was implemented by a large driver-training service provider in China. This system captures and analyzes data streams from onboard sensors and cameras installed in vehicles in real time and immediately provides individual students with information about errors made during simulation tests. We postulate that the focal smart service functions as a feedback intervention (FI) that can improve task performance. We also hypothesize that student training schedules moderate this effect and propose an interaction effect on student performance based on feedback timing and the number of FI cues. We collected data about students’ demographics, their training session records, and information about their simulation test(s) and/or their official driving skills field tests and used a quasi-experimental method along with propensity score matching to empirically validate our research model. Difference-in-difference analysis and multiple regression results support the significant impact of the simulation test as an FI on student performance on the official driving skills field test. Our results also supported the interaction effect between feedback timing and the number of corrective FI cues on official test performance. This paper concludes with a discussion of the theoretical contributions and practical significance of our research

Fast antijamming timing acquisition using multilayer synchronization sequence

Pseudonoise (PN) sequences are widely used as preamble sequences to establish timing synchronization in military wireless communication systems. At the receiver, searching and detection techniques, such as the full parallel search (FPS) and the serial search (SS), are usually adopted to acquire correct timing position. However, the synchronization sequence has to be very long to combat jamming that reduces the signal-to-noise ratio (SNR) to an extremely low level. In this adverse scenario, the FPS scheme becomes too complex to implement, whereas the SS method suffers from the drawback of long mean acquisition time (MAT). In this paper, a fast timing acquisition method is proposed, using the multilayer synchronization sequence based on cyclical codes. Specifically, the transmitted preamble is the Kronecker product of Bose–Chaudhuri-Hocquenghem (BCH) codewords and PN sequences. At the receiver, the cyclical nature of BCH codes is exploited to test only a part of the entire sequence, resulting in shorter acquisition time. The algorithm is evaluated using the metrics of MAT and detection probability (DP). Theoretical expressions of MAT and DP are derived from the constant false-alarm rate (CFAR) criterion. Theoretical analysis and simulation results show that our proposed scheme dramatically reduces the acquisition time while achieving similar DP performance and maintaining a reasonably low real-time hardware implementation complexity, in comparison with the SS schem

Low jitter design techniques for monolithic CMOS phase-locked and delay-locked systems

Timing jitter is a major concern in almost every type of communication system. Yet the desire for high levels of integration works against minimization of this error, especially for systems employing a phase-locked loop (PLL) or delay-locked loop (DLL) for timing generation or timing recovery. There has been an increasing demand for fully-monolithic CMOS PLL and DLL designs with good jitter performance. In this thesis, the system level as well as the transistor level low jitter design techniques for integrated PLLs and DLLs have been explored.;On the system level, a rigorous jitter analysis method based on a z-domain model is developed, in which the jitter is treated as a random event. Combined with statistical methods, the rms value of the accumulated jitter can be expressed with a closed form solution that successfully ties the jitter performance with loop parameters. Based on this analysis, a cascaded PLL/DLL structure is proposed which combines the advantage of both loops. The resulting system is able to perform frequency synthesis with the jitter as low as that of a DLL.;As an efficient tool to predict the jitter performance of a PLL or DLL system, a new nonlinear behavioral simulator is developed based on a novel behavioral modeling of the VCO and delay-line. Compared with prior art, this simulator not only simplifies the computation but also enables the noise simulation. Both jitter performance during tracking and lock condition can be predicted. This is also the first reported top-level simulation tool for DLL noise simulation.;On the transistor level, three prototype chips for different applications were implemented and tested. The first two chips are the application of PLL in Gigabit fibre channel transceivers. High speed circuit blocks that have good noise immunity are the major design concern. Testing results show that both designs have met the specifications with low power dissipation. For the third chip, an adaptive on-chip dynamic skew calibration technique is proposed to realize a precise delay multi-phase clock generator, which is a topic that has not been addressed in previous work thus far. Experimental results strongly support the effectiveness of the calibration scheme. At the same time, this design achieves by far the best reported jitter performance

Optical Time-Transfer for Bistatic SAR Small Spacecraft

A spacecraft-to-spacecraft optical time-transfer simulation has been developed as a tool for informing NASA’s Surface Deformation and Change (SDC) mission architecture. The SDC mission will combine radar images from multiple spacecraft to improve understanding of the Earth’s sea-level and landscape changes. Spacecraft must be precisely synchronized in order to create sharp and phase accurate radar images. Simulation of multiple spacecraft time-synchronizing via laser communication can inform technology choices of a mission by providing sub-nanosecond precision estimates of clock error. This timing and ranging simulation has been combined with a radar system performance analysis pipeline. The simulated timing errors are used in a radar simulation to predict performance of bistatic SAR systems in the presence of oscillator noise and time synchronization inaccuracy. Precision time-transfer techniques facilitate the accurate synchronization of clocks between any combination of terminals. Most time-transfer technology for comparing two clocks at different terminals use radio frequencies (RF) to measure the time delay between the sending and receiving of signals. Laser technology offers the capability to transmit high data rates with systems that are of smaller size and lower power than comparable RF systems. The clocks on independent spacecraft will have some phase and frequency errors between them that result in clock drift. The two clock models that are included in this bi-directional MATLAB simulation are a Microchip Microsemi cesium-based Chip-Scale Atomic Clock (CSAC) and a Microchip Microsemi rubidium-based Miniature Atomic Clock (MAC). The CSAC has flown as hardware for small satellite missions such as the University of Florida’s CHOMPTT mission. A study of an example orbit, based on previous satellite laser ranging (SLR) missions and lasing rates demonstrate the impact of flight configuration parameters on the synchronization error between two spacecraft. The MATLAB timing simulation uses a Runge-Kutta 4th-order method to propagate spacecraft orbits and computes the light-travel time estimate between them. The simulation outputs the estimated clock error based on a user-defined spacecraft cluster configuration. The radar simulation is applied to evaluate a potential future bistatic SAR constellation architecture. In the proposed architecture, satellites follow each other in the same orbit at 500 km altitude, with a 250 km baseline direct line-of-sight between satellites. We also baseline the CSAC as a stable oscillator. We use NASA’s NISAR for baseline radar system parameters, but scale down the simulated antenna and radar power to represent a possible small-satellite platform. We compute a clock-system introduced phase error of 0.17 degrees with our simulated time-transfer architecture. This analysis technique could be extended or modified to evaluate the timing requirements of other geometries for other future multistatic SAR missions, or other interferometric satellite missions