High Speed Clock Glitching

In recent times, hardware security has drawn a lot of interest in the research community. With physical proximity to the target devices, various fault injection hardware attack methods have been proposed and tested to alter their functionality and trigger behavior not intended by the design. There are various types of faults that can be injected depending on the parameters being used and the level at which the device is tampered with. The literature describes various fault models to inject faults in clock of the target but there are no publications on overclocking circuits for fault injection. The proposed method bridges this gap by conducting high-speed clock fault injection on latest high-speed micro-controller units where the target device is overclocked for a short duration in the range of 4-1000 ns. This thesis proposes a method of generating a high-speed clock and driving the target device using the same clock. The properties of the target devices for performing experiments in this research are: Externally accessible clock input line and GPIO line. The proposed method is to develop a high-speed clock using custom bit-stream sent to FPGA and subsequently using external analog circuitry to generate a clock-glitch which can inject fault on the target micro-controller. Communication coupled with glitching allows us to check the target\u27s response, which can result in information disclosure.This is a form of non-invasive and effective hardware attack. The required background, methodology and experimental setup required to implement high-speed clock glitching has been discussed in this thesis. The impact of different overclock frequencies used in clock fault injection is explored. The preliminary results have been discussed and we show that even high-speed micro-controller units should consider countermeasures against clock fault injection. Influencing the execution of Tiva C Launchpad and STM32F4 micro-controller units has been shown in this thesis. The thesis details the method used for the testing a

Passive and Active Combined Attacks on AES Combining Fault Attacks and Side Channel Analysis

International audienc

Assembly Level Clock Glitch Insertion Into An XMega MCU

This thesis proposes clock-glitch fault injection technique to inject glitches into the clock signal running in a microcontroller unit and studying its effects on different assembly level instructions. It focusses mainly on the effect of clock glitches over the execution, sub-execution and pre-execution cycles of the test instructions and also finds the delay between the actual position of glitch insertion and the trigger being set for the glitch insertion. The instructions used in this work are provided by Atmel which classifies them according to their type of operation. These instructions are here further grouped depending on the number of clock cycles they require for their execution. Each group of instructions are tested for their behavior towards clock glitches being injected at different places in and surrounding their execution cycle. This thesis utilizes the ChipWhisperer-Lite board (CW1173) for performing the whole experiment by controlling the target device, providing clock as well as clock glitches with appropriate properties at appropriate position to the target device. The Atmel AVR XMEGA 128D4U is used as the target device (CW303) that uses an external clock of frequency 7.37MHz generated by the main board. The Capture software, provided by the ChipWhisperer, is used for establishing the hardware connection between the main board and the target board. The clock glitches are designed and triggered through the Capture software

Assembly Level Clock Glitch Insertion Into An XMega MCU

This thesis proposes clock-glitch fault injection technique to inject glitches into the clock signal running in a microcontroller unit and studying its effects on different assembly level instructions. It focusses mainly on the effect of clock glitches over the execution, sub-execution and pre-execution cycles of the test instructions and also finds the delay between the actual position of glitch insertion and the trigger being set for the glitch insertion. The instructions used in this work are provided by Atmel which classifies them according to their type of operation. These instructions are here further grouped depending on the number of clock cycles they require for their execution. Each group of instructions are tested for their behavior towards clock glitches being injected at different places in and surrounding their execution cycle. This thesis utilizes the ChipWhisperer-Lite board (CW1173) for performing the whole experiment by controlling the target device, providing clock as well as clock glitches with appropriate properties at appropriate position to the target device. The Atmel AVR XMEGA 128D4U is used as the target device (CW303) that uses an external clock of frequency 7.37MHz generated by the main board. The Capture software, provided by the ChipWhisperer, is used for establishing the hardware connection between the main board and the target board. The clock glitches are designed and triggered through the Capture software

ASSESSING AND IMPROVING THE RELIABILITY AND SECURITY OF CIRCUITS AFFECTED BY NATURAL AND INTENTIONAL FAULTS

The reliability and security vulnerability of modern electronic systems have emerged as concerns due to the increasing natural and intentional interferences. Radiation of high-energy charged particles generated from space environment or packaging materials on the substrate of integrated circuits results in natural faults. As the technology scales down, factors such as critical charge, voltage supply, and frequency change tremendously that increase the sensitivity of integrated circuits to natural faults even for systems operating at sea level. An attacker is able to simulate the impact of natural faults and compromise the circuit or cause denial of service. Therefore, instead of utilizing different approaches to counteract the effect of natural and intentional faults, a unified countermeasure is introduced. The unified countermeasure thwarts the impact of both reliability and security threats without paying the price of more area overhead, power consumption, and required time. This thesis first proposes a systematic analysis method to assess the probability of natural faults propagating the circuit and eventually being latched. The second part of this work focuses on the methods to thwart the impact of intentional faults in cryptosystems. We exploit a power-based side-channel analysis method to analyze the effect of the existing fault detection methods for natural faults on fault attack. Countermeasures for different security threats on cryptosystems are investigated separately. Furthermore, a new micro-architecture is proposed to thwart the combination of fault attacks and side-channel attacks, reducing the fault bypass rate and slowing down the key retrieval speed. The third contribution of this thesis is a unified countermeasure to thwart the impact of both natural faults and attacks. The unified countermeasure utilizes dynamically alternated multiple generator polynomials for the cyclic redundancy check (CRC) codec to resist the reverse engineering attack

Optimisation de la réponse aux menaces basée sur les coûts dans des systèmes pour la Sécurité de l'Information et la Gestion des Evénements (SIEMs)

Les SIEMs (systèmes pour la Sécurité de l'Information et la Gestion des Evénements) sont le cœur des centres opérationnels de sécurité actuels. Les SIEMs corrèlent les événements en provenance de différents capteurs (anti-virus, pare-feux, systèmes de détection d'intrusion, etc), et offrent des vues synthétiques pour la gestion des menaces ainsi que des rapports de sécurité. La recherche dans les technologies SIEM a toujours mis l'accent sur la fourniture d'une interprétation complète des menaces, en particulier pour évaluer leur importance et hiérarchiser les réponses. Toutefois, dans de nombreux cas, la réponse des menaces a encore besoin de l'homme pour mener l'analyse et aboutir à la prise de décisions, p.ex. compréhension des menaces, définition des contremesures appropriées ainsi que leur déploiement. Il s'agit d'un processus lent et coûteux, nécessitant un haut niveau d'expertise, qui reste néanmoins sujet à erreurs. Ainsi, des recherches récentes sur les SIEMs ont mis l'accent sur l'importance et la capacité d'automatiser le processus de sélection et le déploiement des contremesures. Certains auteurs ont proposé des mécanismes automatiques de réponse, comme l'adaptation des politiques de sécurité pour dépasser les limites de réponses statiques ou manuelles. Bien que ces approches améliorent le processus de réaction (en le rendant plus rapide et/ou plus efficace), ils restent limités car ces solutions n'analysent pas l'impact des contremesures choisies pour atténuer les attaques. Dans cette thèse, nous proposons une nouvelle approche systématique qui sélectionne la contremesure optimale au travers d'un ensemble de candidats, classés sur la base d'une comparaison entre leur efficacité à arrêter l'attaque et leur capacité à préserver, simultanément, le meilleur service aux utilisateurs légitimes. Nous proposons également un modèle pour représenter graphiquement les attaques et les contre-mesures, afin de déterminer le volume de chaque élément dans un scénario de multiples attaques. Les coordonnées de chaque élément sont dérivés d'un URI . Ce dernier est composé principalement de trois axes : l utilisateur, le canal et le ressource. Nous utilisons la méthodologie CARVER pour donner un poids approprié à chaque élément composant les axes de notre système de coordonnées. Cette approche nous permet de connecter les volumes avec les risques (p.ex. des grands volumes sont équivalents à des risques élevés, tandis que des petits volumes sont équivalents à des risques faibles). Deux concepts sont considérés en comparant deux ou plusieurs volumes de risques: le risque résiduel, qui résulte lorsque le volume du risque est plus élevé que le volume de la contre-mesure, et le dommage collatéral, qui en résulte lorsque le volume de la contre-mesure est supérieur au volume du risque. En conséquence, nous sommes en mesure d'évaluer les contre-mesures pour des scénarios d'attaques individuelles et multiples, ce qui permet de sélectionner la contre-mesure ou groupe de contre-mesures qui fournit le plus grand bénéfice à l'organisationCurrent Security Information and Event Management systems (SIEMs) constitute the central platform of modern security operating centers. They gather events from various sensors (intrusion detection systems, anti-virus, firewalls, etc.), correlate these events, and deliver synthetic views for threat handling and security reporting. Research in SIEM technologies has traditionally focused on providing a comprehensive interpretation of threats, in particular to evaluate their importance and prioritize responses accordingly. However, in many cases, threat responses still require humans to carry out the analysis and decision tasks e.g., understanding the threats, defining the appropriate countermeasures and deploying them. This is a slow and costly process, requiring a high level of expertise, and remaining error-prone nonetheless. Thus, recent research in SIEM technology has focused on the ability to automate the process of selecting and deploying countermeasures. Several authors have proposed automatic response mechanisms, such as the adaptation of security policies, to overcome the limitations of static or manual response. Although these approaches improve the reaction process (making it faster and/or more efficient), they remain limited since these solutions do not analyze the impact of the countermeasures selected to mitigate the attacks. In this thesis, we propose a novel and systematic process to select the optimal countermeasure from a pool of candidates, by ranking them based on a trade-off between their efficiency in stopping the attack and their ability to preserve, at the same time, the best service to normal users. In addition, we propose a model to represent graphically attacks and countermeasures, so as to determine the volume of each element in a scenario of multiple attacks. The coordinates of each element are derived from a URI. This latter is mainly composed of three axes: user, channel, and resource. We use the CARVER methodology to give an appropriate weight to each element composing the axes in our coordinate system. This approach allows us to connect the volumes with the risks (i.e. big volumes are equivalent to high risk, whereas small volumes are equivalent to low risk). Two concepts are considered while comparing two or more risk volumes: Residual risk, which results when the risk volume is higher than the countermeasure volume; and Collateral damage, which results when the countermeasure volume is higher than the risk volume. As a result, we are able to evaluate countermeasures for single and multiple attack scenarios, making it possible to select the countermeasure or group of countermeasures that provides the highest benefit to the organizationEVRY-INT (912282302) / SudocSudocFranceF