Parametric Macromodels of Differential Drivers and Receivers

This paper addresses the modeling of differential drivers and receivers for the analog simulation of high-speed interconnection systems. The proposed models are based on mathematical expressions, whose parameters can be estimated from the transient responses of the modeled devices. The advantages of this macromodeling approach are: improved accuracy with respect to models based on simplified equivalent circuits of devices; improved numerical efficiency with respect to detailed transistor-level models of devices; hiding of the internal structure of devices; straightforward circuit interpretation; or implementations in analog mixed-signal simulators. The proposed methodology is demonstrated on example devices and is applied to the prediction of transient waveforms and eye diagrams of a typical low-voltage differential signaling (LVDS) data link

On the Behavioral Modeling of Integrated Circuit Output Buffers

The properties of common behavioral macromodels for single ended CMOS integrated circuits output buffers are discussed with the aim of providing criteria for an effective use of possible modeling options

Parametric Macromodels of Digital I/O Ports

This paper addresses the development of macromodels for input and output ports of a digital device. The proposed macromodels consist of parametric representations that can be obtained from port transient waveforms at the device ports via a well established procedure. The models are implementable as SPICE subcircuits and their accuracy and efficiency are verified by applying the approach to the characterization of transistor-level models of commercial devices

M[pi]log, Macromodeling via parametric identification of logic gates

This paper addresses the development of computational models of digital integrated circuit input and output buffers via the identification of nonlinear parametric models. The obtained models run in standard circuit simulation environments, offer improved accuracy and good numerical efficiency, and do not disclose information on the structure of the modeled devices. The paper reviews the basics of the parametric identification approach and illustrates its most recent extensions to handle temperature and supply voltage variations as well as power supply ports and tristate devices

Parametric Macromodels of Digital I/O Ports

This paper addresses the development of macromodels for input and output ports of a digital device. The proposed macromodels consist of parametric representations that can be obtained from port transient waveforms at the device ports via a well established procedure. The models are implementable as SPICE subcircuits and their accuracy and efficiency are verified by applying the approach to the characterization of transistor-level models of commercial devices

Behavioral Models of I/O Ports from Measured Transient Waveforms

This paper addresses the development of accurate and efficient behavioral models of digital integrated circuit ports from measured transient responses. The proposed approach is based on the estimation of parametric models from port voltage and current waveforms. The modeling process is described and applied to the modeling of output ports. Its feasibility is demonstrated by the identification of a real device from actual measurements, and by the comparison of the predicted device response with the measured one

Automated nonlinear Macromodelling of output buffers for high-speed digital applications

We present applications of a recently developed automated nonlin-ear macromodelling approach to the important problem of macro-modelling high-speed output buffers/drivers. Good nonlinear macro-models of such drivers are essential for fast signal-integrity and timing analysis in high-speed digital design. Unlike traditional black-box modelling techniques, our approach extracts nonlinear macromodels of digital drivers automatically from SPICE-level de-scriptions. Thus it can naturally capture transistor-level nonlinear-ities in the macromodels, resulting in far more accurate signal in-tegrity analysis, while retaining significant speedups. We demon-strate the technique by automatically extracting macromodels for two typical digital drivers. Using the macromodel, we obtain about 8 × speedup in average with excellent accuracy in capturing differ-ent loading effects, crosstalk, simultaneous switching noise (SSN), etc.

Macromodel Extraction for Drivers in High-Speed Communications Channels

Proyecto de Graduación (Licenciatura en Ingeniería Electrónica) Instituto Tecnológico de Costa Rica, Escuela de Ingeniería Electrónica, 2015.This thesis describes the process performed for extracting a descriptive macromodel for a generic transmitter block at IC level for high-speed channels applications. The work has been focused on a first approach to establish at methodology to extract a macromodel considering both the signal and power domains. Macromodels are required to perform accurate and numerically efficient simulations, in order to verify and validate behavior performances of communication links without having to consider the full driver model and potential IP sensitive information related to it. In this work, different approaches for macromodeling generation are reviewed and a methodology based on the IBIS specification is explored. A driver specific topology had been chosen in order to exercise the methodology for macromodel generation. An important feature of the methodology is the possibility to include the effects concerning signal integrity and power integrity simultaneously, which was carried out by including controlled sources on the output of the driver

Investigation of Interconnect and Device Designs for Emerging Post-MOSFET and Beyond Silicon Technologies

Title from PDF of title page viewed May 31, 2017Dissertation advisor: Masud H. ChowdhuryVitaIncludes bibliographical references (pages 94-108)Thesis (Ph.D.)--School of Computing and Engineering and Department of Physics and Astronomy. University of Missouri--Kansas City, 2016The integrated circuit industry has been pursuing Moore’s curve down to deep nanoscale dimensions that would lead to the anticipated delivery of 100 billion transistors on a 300 mm² die operating below 1V supply in the next 5-10 years. However, the grand challenge is to reliably and efficiently take the full advantage of the unprecedented computing power offered by the billions of nanoscale transistors on a single chip. To mitigate this challenge, the limitations of both the interconnecting wires and semiconductor devices in integrated circuits have to be addressed. At the interconnect level, the major challenge in current high density integrated circuit is the electromagnetic and electrostatic impacts in the signal carrying lines. Addressing these problems require better analysis of interconnect resistance, inductance, and capacitance. Therefore, this dissertation has proposed a new delay model and analyzed the time-domain output response of complex poles, real poles, and double poles for resistance-inductance capacitance interconnect network based on a second order approximate transfer function. Both analytical models and simulation results show that the real poles model is much faster than the complex poles model, and achieves significantly higher accuracy in order to characterize the overshoot and undershoot of the output responses. On the other hand, the semiconductor industry is anticipating that within a decade silicon devices will be unable to meet the demands at nanoscale due to dimension and material scaling. Recently, molybdenum disulfide (MoS₂) has emerged as a new super material to replace silicon in future semiconductor devices. Besides, conventional field effect transistor technology is also reaching its thermodynamic limit. Breaking this thermal and physical limit requires adoption of new devices based on tunneling mechanism. Keeping the above mentioned trends, this dissertation also proposed a multilayer MoS₂ channel-based tunneling transistor and identifies the fundamental parameters and design specifications that need to be optimized in order to achieve higher ON-currents. A simple analytical model of the proposed device is derived by solving the time-independent Schrodinger equation. It is analytically proven that the proposed device can offer an ON-current of 80 A/m, a subthreshold swing (S) of 9.12 mV/decade, and a / ratio of 10¹².Introduction -- Previous models on interconnect designs -- Proposed delay model for interconnect design -- Investigation of tunneling for field effect transistor -- Study of molybdenum disulfide for FET applications -- Proposed molybdenum disulfide based tunnel transistor -- Conclusion -- Appendix A. Derivation of time delay model -- Appendix B. Derivation of tunneling current model Appendix C. Derivation of subthreshold swing mode