Efficient Design of Triplet Based Spike-Timing Dependent Plasticity

Spike-Timing Dependent Plasticity (STDP) is believed to play an important role in learning and the formation of computational function in the brain. The classical model of STDP which considers the timing between pairs of pre-synaptic and post-synaptic spikes (p-STDP) is incapable of reproducing synaptic weight changes similar to those seen in biological experiments which investigate the effect of either higher order spike trains (e.g. triplet and quadruplet of spikes), or, simultaneous effect of the rate and timing of spike pairs on synaptic plasticity. In this paper, we firstly investigate synaptic weight changes using a p-STDP circuit and show how it fails to reproduce the mentioned complex biological experiments. We then present a new STDP VLSI circuit which acts based on the timing among triplets of spikes (t-STDP) that is able to reproduce all the mentioned experimental results. We believe that our new STDP VLSI circuit improves upon previous circuits, whose learning capacity exceeds current designs due to its capability of mimicking the outcomes of biological experiments more closely; thus plays a significant role in future VLSI implementation of neuromorphic systems

Modeling triplet spike-timing-dependent plasticity using memristive devices

Triplet-based spike-timing-dependent plasticity (TSTDP) is an advanced synaptic plasticity rule that results in improved learning capability compared to the conventional pair-based STDP (PSTDP). The TSTDP rule can reproduce the results of many electrophysiological experiments, where the PSTDP fails. This paper proposes a novel memristive circuit that implements the TSTDP rule. The proposed circuit is designed using three voltage (flux)-driven memristors. Simulation results demonstrate that our memristive circuit induces synaptic weight changes that arise due to the timing differences among pairs and triplets of spikes. The presented memristive design is an initial step toward developing asynchronous TSTDP learning architectures using memristive devices. These architectures may facilitate the implementation of advanced large-scale neuromorphic systems with applications in real-world engineering tasks such as pattern classification

A Comprehensive Workflow for General-Purpose Neural Modeling with Highly Configurable Neuromorphic Hardware Systems

In this paper we present a methodological framework that meets novel requirements emerging from upcoming types of accelerated and highly configurable neuromorphic hardware systems. We describe in detail a device with 45 million programmable and dynamic synapses that is currently under development, and we sketch the conceptual challenges that arise from taking this platform into operation. More specifically, we aim at the establishment of this neuromorphic system as a flexible and neuroscientifically valuable modeling tool that can be used by non-hardware-experts. We consider various functional aspects to be crucial for this purpose, and we introduce a consistent workflow with detailed descriptions of all involved modules that implement the suggested steps: The integration of the hardware interface into the simulator-independent model description language PyNN; a fully automated translation between the PyNN domain and appropriate hardware configurations; an executable specification of the future neuromorphic system that can be seamlessly integrated into this biology-to-hardware mapping process as a test bench for all software layers and possible hardware design modifications; an evaluation scheme that deploys models from a dedicated benchmark library, compares the results generated by virtual or prototype hardware devices with reference software simulations and analyzes the differences. The integration of these components into one hardware-software workflow provides an ecosystem for ongoing preparative studies that support the hardware design process and represents the basis for the maturity of the model-to-hardware mapping software. The functionality and flexibility of the latter is proven with a variety of experimental results

Emergent Auditory Feature Tuning in a Real-Time Neuromorphic VLSI System

Many sounds of ecological importance, such as communication calls, are characterized by time-varying spectra. However, most neuromorphic auditory models to date have focused on distinguishing mainly static patterns, under the assumption that dynamic patterns can be learned as sequences of static ones. In contrast, the emergence of dynamic feature sensitivity through exposure to formative stimuli has been recently modeled in a network of spiking neurons based on the thalamo-cortical architecture. The proposed network models the effect of lateral and recurrent connections between cortical layers, distance-dependent axonal transmission delays, and learning in the form of Spike Timing Dependent Plasticity (STDP), which effects stimulus-driven changes in the pattern of network connectivity. In this paper we demonstrate how these principles can be efficiently implemented in neuromorphic hardware. In doing so we address two principle problems in the design of neuromorphic systems: real-time event-based asynchronous communication in multi-chip systems, and the realization in hybrid analog/digital VLSI technology of neural computational principles that we propose underlie plasticity in neural processing of dynamic stimuli. The result is a hardware neural network that learns in real-time and shows preferential responses, after exposure, to stimuli exhibiting particular spectro-temporal patterns. The availability of hardware on which the model can be implemented, makes this a significant step toward the development of adaptive, neurobiologically plausible, spike-based, artificial sensory systems

CMOS and memristive hardware for neuromorphic computing

The ever-increasing processing power demands of digital computers cannot continue to be fulfilled indefinitely unless there is a paradigm shift in computing. Neuromorphic computing, which takes inspiration from the highly parallel, low power, high speed, and noise-tolerant computing capabilities of the brain, may provide such a shift. To that end, various aspects of the brain, from its basic building blocks, such as neurons and synapses, to its massively parallel in-memory computing networks have been being studied by the huge neuroscience community. Concurrently, many researchers from across academia and industry have been studying materials, devices, circuits, and systems, to implement some of the functions of networks of neurons and synapses to develop bio-inspired (neuromorphic) computing platforms

Metal Oxide Memristors with Internal Dynamics for Neuromorphic Applications

Metal oxide memristors, a two-terminal nanoscale semiconductor device whose resistance/conductance can be regulated according to the history of applied stimulations, are initially proposed as a promising candidate for the next generation non-volatile memory. Bearing the similarity to the weight change of synapses in human brain, they are recently being intensively investigated as a critical component in neural network for neuromorphic applications. The resistive switching mechanism is attributed to the redistribution of oxygen vacancies under electric field and spontaneous diffusion. Based on this understanding, 2nd order switching dynamics is discovered and thoroughly investigated for the first time in both WOx memristor and Ta2O5-TaOx memristor and more comprehensive resistive switching models are proposed to quantitively capture the internal ionic dynamics. The dynamics is utilized to implement important synaptic functions including paired pulse facilitation, spike-timing dependent plasticity, experience dependent plasticity, in single cell and in a bio-realistic fashion. WOx memristor crossbar network is used to implement several important neuromorphic applications including: 1) sparse coding, as the network can easily conduct matrix operation, especially dot product and the resistance of each cell at the crosspoint can be regulated to store information needed for computation, 2) temporal information processing through memristor-based liquid state machine, as WOx memristor has the ability to process temporal information due to its short-term memory which is caused by its spontaneous decay characteristics. Improvement of both single cell performance towards better synaptic behaviors and memristor crossbar network performance for large scale applications are achieved by the optimization of fabrication methods.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/137133/1/chdu_1.pd

Phenomenological modeling of diverse and heterogeneous synaptic dynamics at natural density

This chapter sheds light on the synaptic organization of the brain from the perspective of computational neuroscience. It provides an introductory overview on how to account for empirical data in mathematical models, implement them in software, and perform simulations reflecting experiments. This path is demonstrated with respect to four key aspects of synaptic signaling: the connectivity of brain networks, synaptic transmission, synaptic plasticity, and the heterogeneity across synapses. Each step and aspect of the modeling and simulation workflow comes with its own challenges and pitfalls, which are highlighted and addressed in detail.Comment: 35 pages, 3 figure

Optimisation de réseaux de neurones à décharges avec contraintes matérielles pour processeur neuromorphique

Les modèles informatiques basés sur l'apprentissage machine ont démarré la seconde révolution de l'intelligence artificielle. Capables d'atteindre des performances que l'on crut inimaginables au préalable, ces modèles semblent devenir partie courante dans plusieurs domaines. La face cachée de ceux-ci est que l'énergie consommée pour l'apprentissage, et l'utilisation de ces techniques, est colossale. La dernière décennie a été marquée par l'arrivée de plusieurs processeurs neuromorphiques pouvant simuler des réseaux de neurones avec une faible consommation d'énergie. Ces processeurs offrent une alternative aux conventionnelles cartes graphiques qui demeurent à ce jour essentielles au domaine. Ces processeurs sont capables de réduire la consommation d'énergie en utilisant un modèle de neurone événementiel, plus communément appelé neurone à décharge. Ce type de neurone est fondamentalement différent du modèle classique, et possède un aspect temporel important. Les méthodes, algorithmes et outils développés pour le modèle de neurone classique ne sont pas adaptés aux neurones à décharges. Cette thèse de doctorat décrit plusieurs approches fondamentales, dédiées à la création de processeurs neuromorphiques analogiques, qui permettent de pallier l'écart existant entre les systèmes à base de neurones conventionnels et à décharges. Dans un premier temps, nous présentons une nouvelle règle de plasticité synaptique permettant l'apprentissage non supervisé des réseaux de neurones récurrents utilisant ce nouveau type de neurone. Puis, nous proposons deux nouvelles méthodes pour la conception des topologies de ce même type de réseau. Finalement, nous améliorons les techniques d'apprentissage supervisé en augmentant la capacité de mémoire de réseaux récurrents. Les éléments de cette thèse marient l'inspiration biologique du cerveau, l'ingénierie neuromorphique et l'informatique fondamentale pour permettre d'optimiser les réseaux de neurones pouvant fonctionner sur des processeurs neuromorphiques analogiques