The Miniaturization of the AFIT Random Noise Radar

Advances in technology and signal processing techniques have opened the door to using an UWB random noise waveform for radar imaging. This unique, low probability of intercept waveform has piqued the interest of the U.S. DoD as well as law enforcement and intelligence agencies alike. While AFIT\u27s noise radar has made significant progress, the current architecture needs to be redesigned to meet the space constraints and power limitations of an aerial platform. This research effort is AFIT\u27s first attempt at RNR miniaturization and centers on two primary objectives: 1) identifying a signal processor that is compact, energy efficient, and capable of performing the demanding signal processing routines and 2) developing a high-speed correlation algorithm that is suited for the target hardware. A correlation routine was chosen as the design goal because of its importance to the noise radar\u27s ability to estimate the presence of a return signal. Furthermore, it is a computationally intensive process that was used to determine the feasibility of the processing component. To determine the performance of the proposed algorithm, results from simulation and experiments involving representative hardware were compared to the current system. Post-implementation reports of the FPGA-based correlator indicated zero timing failures, less than a Watt of power consumption, and a 44% utilization of the Virtex-5\u27s logic resources

Fast Fourier transforms on energy-efficient application-specific processors

Many of the current applications used in battery powered devices are from digital signal processing, telecommunication, and multimedia domains. Traditionally application-specific fixed-function circuits have been used in these designs in form of application-specific integrated circuits (ASIC) to reach the required performance and energy-efficiency. The complexity of these applications has increased over the years, thus the design complexity has increased even faster, which implies increased design time. At the same time, there are more and more standards to be supported, thus using optimised fixed-function implementations for all the functions in all the standards is impractical. The non-recurring engineering costs for integrated circuits have also increased significantly, so manufacturers can only afford fewer chip iterations. Although tailoring the circuit for a specific application provides the best performance and/or energy-efficiency, such approach lacks flexibility. E.g., if an error is found after the manufacturing, an expensive chip iteration is required. In addition, new functionalities cannot be added afterwards to support evolution of standards. Flexibility can be obtained with software based implementation technologies. Unfortunately, general-purpose processors do not provide the energy-efficiency of the fixed-function circuit designs. A useful trade-off between flexibility and performance is implementation based on application-specific processors (ASP) where programmability provides the flexibility and computational resources customised for the given application provide the performance. In this Thesis, application-specific processors are considered by using fast Fourier transform as the representative algorithm. The architectural template used here is transport triggered architecture (TTA) which resembles very long instruction word machines but the operand execution resembles data flow machines rather than traditional operand triggering. The developed TTA processors exploit inherent parallelism of the application. In addition, several characteristics of the application have been identified and those are exploited by developing customised functional units for speeding up the execution. Several customisations are proposed for the data path of the processor but it is also important to match the memory bandwidth to the computation speed. This calls for a memory organisation supporting parallel memory accesses. The proposed optimisations have been used to improve the energy-efficiency of the processor and experiments show that a programmable solution can have energy-efficiency comparable to fixed-function ASIC designs

Optimum Circuits for Bit Reversal

This brief presents novel circuits for calculating bit reversal on a series of data. The circuits are simple and consist of buffers and multiplexers connected in series. The circuits are optimum in two senses: they use the minimum number of registers that are necessary for calculating the bit reversal and have minimum latency. This makes them very suitable for calculating the bit reversal of the output frequencies in hardware fast Fourier transform (FFT) architectures. This brief also proposes optimum solutions for reordering the output frequencies of the FFT when different common radices are used, including radix-2, radix-2(k), radix-4, and radix-8.Funding Agencies|Spanish Ministry of Education|AP2005-0544|Spanish National Research and Development Program|TEC2008-02148|Swedish ELLIIT Program||</p