Scalable Design and Synthesis of Reversible Circuits

The expectations on circuits are rising with their number of applications, and technologies alternative to CMOS are becoming more important day by day. A promising alternative is reversible computation, a computing paradigm with applications in quantum computation, adiabatic circuits, program inversion, etc. An elaborated design flow is not available to reversible circuit design yet. In this work, two directions are considered: Exploiting the conventional design flow and developing a new flow according to the properties of reversible circuits. Which direction should be taken is not obvious, so we discuss the possible assets and drawbacks of taking either direction. We present ideas which can be exploited and outline open challenges which still have to be addressed. Preliminary results obtained by initial implementations illustrate the way to go. By this we present and discuss two promising and complementary directions for the scalable design and synthesis of reversible circuits

Synthesis and Optimization of Reversible Circuits - A Survey

Reversible logic circuits have been historically motivated by theoretical research in low-power electronics as well as practical improvement of bit-manipulation transforms in cryptography and computer graphics. Recently, reversible circuits have attracted interest as components of quantum algorithms, as well as in photonic and nano-computing technologies where some switching devices offer no signal gain. Research in generating reversible logic distinguishes between circuit synthesis, post-synthesis optimization, and technology mapping. In this survey, we review algorithmic paradigms --- search-based, cycle-based, transformation-based, and BDD-based --- as well as specific algorithms for reversible synthesis, both exact and heuristic. We conclude the survey by outlining key open challenges in synthesis of reversible and quantum logic, as well as most common misconceptions.Comment: 34 pages, 15 figures, 2 table

Heuristic Synthesis of Reversible Logic – A Comparative Study

Reversible logic circuits have been historically motivated by theoretical research in low-power, and recently attracted interest as components of the quantum algorithm, optical computing and nanotechnology. However due to the intrinsic property of reversible logic, traditional irreversible logic design and synthesis methods cannot be carried out. Thus a new set of algorithms are developed correctly to synthesize reversible logic circuit. This paper presents a comprehensive literature review with comparative study on heuristic based reversible logic synthesis. It reviews a range of heuristic based reversible logic synthesis techniques reported by researchers (BDD-based, cycle-based, search-based, non-search-based, rule-based, transformation-based, and ESOP-based). All techniques are described in detail and summarized in a table based on their features, limitation, library used and their consideration metric. Benchmark comparison of gate count and quantum cost are analysed for each synthesis technique. Comparing the synthesis algorithm outputs over the years, it can be observed that different approach has been used for the synthesis of reversible circuit. However, the improvements are not significant. Quantum cost and gate count has improved over the years, but arguments and debates are still on certain issues such as the issue of garbage outputs that remain the same. This paper provides the information of all heuristic based synthesis of reversible logic method proposed over the years. All techniques are explained in detail and thus informative for new reversible logic researchers and bridging the knowledge gap in this area

Minimization of lines in reversible circuits

Reversible computing has been theoretically shown to be an efficient approach over conventional computing due to the property of virtually zero power dissipation. A major concern in reversible circuits is the number of circuit lines or qubits which are a limited resource. In this thesis we explore the line reduction problem using a decision diagram based synthesis approach and introduce a line reduction algorithm— Minimization of lines using Ordered Kronecker Functional Decision Diagrams (MOKFDD). The algorithm uses a new sub-circuit for a positive Davio node structure in addition to the existing node structures. We also present a shared node ordering for OKFDDs. OKFDDs are a combination of OBDDs and OFDDs. The experimental results shows that the number of circuit lines and quantum cost can be reduced with our proposed approach.NSER

Quantum Circuit Synthesis

Tez (Yüksek Lisans) -- İstanbul Teknik Üniversitesi, Fen Bilimleri Enstitüsü, 2015Thesis () -- İstanbul Technical University, Institute of Science and Technology, 2015Bu tez, tersinir devre sentezine dayalı kuantum devrelerin sentezlenmesi için yeni bir yöntem sunmaktadır. Kuantum bilgisayarlar, özellikle kuantum devrelerle oluşturulan kauntum algoritmalar, hesaplamalı alanda vaat ettikleriyle son yıllarda dikkatleri üzerine çekti. Bu bilgisayarlar, klasik bilgisayarların çözemediği kompleks problemleri hesaplamanın önünü açmaktadır. Geleneksel olarak bilgisayarlar 0 veya 1 değeri alabilen bitler ile hesaplamaları gerçekleştirirler. Bitler ile hesaplama genel anlamda oldukça etkin ve verimli olmasına rağmen bazı önemli problemlerin çözümünde yetersiz kalmaktadır. Bunun en önemli nedeni ise bitlerin deterministik olarak çalışması, yani belirli bir zaman aralığında sadece 0 veya 1 değeri alabilmesidir. Richard Feynman tarafından önerilen kuantum bilgisayar fikri, kuantum mekaniğinden faydalanarak hesaplama işlemlerini gerçekleştirme mantığına dayanmaktadır. Bu hesaplama yönteminde, veri saklama elemanları “kübit” olarak adlandırılır. Kuantum mekaniğinin süperpozisyon prensibi gereği, kübitler 0 veya 1 aynı anda hem 0 hem 1 konumunda bulunabilir. Bir başka deyişle bir kübitin değeri, 0 veya 1 olma olasılığını belirtir. Böylece, pratik limitler dahilinde olanaksız olan bir çok problem, kuantum algoritmaları ile rahatlıkla çözebilmektedir. Bu problemlerin belki de en ünlüsü kriptolojide yaygın kullanılan yarı-asal sayıların çarpanlarına ayrılmasıdır. Shor’un kübit tabanlı çarpanlara ayırma algoritması, geleneksel anlamda çözümü yüzyıllar süren durumları, hızlıca çözmektedir. Kuantum devreler, kübitler üzerinde işlem yapan kuantum kapılar kullanılarak inşa edilir. Kuantum devrelerin en önemli özelliklerinden birisi aynı zamanda tersinir (reversible) devreler olmalarıdır. Bu devrelerde, devrenin girişindeki ve çıkışındaki bit sayısı eşittir. Devrenin çıkışındaki değerler bize devrenin girişindeki değerler hakkında bilgi verir. Bu sayede devreleri çift yönlü olarak kullanabilmemize imkan sağlarlar. Tersinir devrelerin en büyük getirisi, bilgisayarlarda yüksek enerji tasarrufuna olanak sağlamalarıdır. Kuantum bilgisayarlar ile ilgili yapılan deneysel uygulamalar her ne kadar emekleme aşamasında olsa da, kuantum hesaplamanın uygulanabilir olduğunu göstermektedir. Bu noktada kuantum hesaplamanın en önemli bölümü olan kuantum devre tasarımı ön plana çıkmaktadır. Çalışmalar en az sayıda kapı kullanarak optimum devreleri sentezlemeyi amaçlamaktadır. Optimize edilmiş devreler, bir yandan güvenilirliği artırırken, diğer bir yandan çalışma süresini düşürmektedir. Şuana kadar yapılan çalışmalarda, optimum devre sentezi sadece 4 bite kadar gerçekleştirildi. Son yapılan ve 84 kübit kullanılan deneyler göz önüne alındığında, optimal devre sentezi pratik olmaktan oldukça uzak kalmaktadır. Bu, çalışmamızı hızlı sentezleme algoritmalarına yönelten motivasyonların başında gelmektedir. Literatürdeki birkaç çalışmada, özellikle yüksek bit sayısı ile sentezleme yapılanlarda, “garbage output” birimleri kullanılmıştır. Bu birimler, ihtiyaç olduğunda kullanılmak üzere devrede fazladan bulundurulan veri yolları olarak düşünülebilir. Bir çok yöntemde, enerji verimililiği ile ilgili problemlerinden ötürü kullanımı düşünülmemiştir. Bu nedenle çalışmamızda “garbage ouput” kullanmadık. Önerdiğimiz yöntem, istenilen fonksiyonu kuantum kapıları kullanarak verimli bir şekilde elde etmekte ve bunu iki ana aşamada yapmaktadır. İlk aşamada, permütasyona dayalı bir algoritma ile seçilen bit büyüklüğüne göre optimum sayıda kapı kullanılan “temel fonksiyonlar” sentezlenmektedir. Her temel fonksiyon için, en az kapı sayısından başlayıp, tüm kapıları ve permütasyonlarını deneyerek, fonksiyonu gerçekleştiren devreyi temel fonksiyonlar kütüphanesine ekler ve bir sonraki temel fonksiyonu aramaya başlar. Kütüphane tamamlandıktan sonra sıralama aşamasına geçilmektedir. Algoritmanın bu aşaması, en çok vakit alan kısım olmasına rağmen, temel fonksiyonların sayısının azlığı ve sıralama algoritmasının hızı, bu yöntemi literatürdeki çalışmalardan oldukça hızlı kılmaktadır. Optimum çözüm üretmeyen yöntemlerle bu devreler çok daha hızlı bir şekilde elde edilebilir ancak devre maliyetleri çok daha yüksek olacaktır. Temel fonksiyonların maliyetleri, oluşturulacak olan tüm devrelerin maliyetini etkileyeceğinden, devreleri optimum olarak sentezlemeyi tercih ettik. Devre sentezleme aşaması, istenilen fonksiyonu elde etmemizi sağlayan sıralama süreci ile devam eder. Bu süreç, algoritmamıza hızını kazandıran, yöntemimizin en önemli bölümdür. Sıralama algoritmaları, matematik ve bilgisayar biliminde uzun süredir çalışılan bir konu olduğundan, birçok farklı sıralama algoritması geliştirilmiştir. Biz çalışmamızda, “Seçmeli Sıralama” algoritmasını kullandık. Bu sıralama yöntemi, verilen fonksiyonu, doğruluk tablosu ile karşılaştırarak satır satır kontrol edip, eşleşmeyen her durum için temel fonksiyonlardan birini kullanarak, fonksiyonu adım adım birim fonksiyona çevirmektedir. Diğer sıralama algoritmalarının aksine kaydırma veya bölme işlemlerini uygulamadığından, fazladan temel fonksiyon kullanımını önleyerek, devre maliyetini düşük tutmaktadır. Örneğin, birleştirmeli sıralama, verilen sıralama kümesini öncelikle alt kümelere ayırıp, bu alt kümeleri sıralamaktadır. Ardından, oluşturulan alt kümeler, parça parça birleştirilerek her yeni birleşmede yeni bir sıralama yapılmaktadır. Sıralamalardaki yer değiştirme işlemlerinin her biri ek bir temel fonksiyon kullanımına neden olmaktadır. Aynı şekilde, eklemeli sıralama algoritmasında kullanılan kaydırma işlemlerinin her biri, bir temel fonksiyona karşılık gelmektedir. Seçmeli algoritma ile oluşturulan devrelerin maliyeti, yerdeğiştirilecek olan satırların değiştirilme sırasının, doğru bir şekilde belirlenmesiyle iyileştirilebileceğini gösterdik. Bu amaçla, çalışmamıza her fonksiyon için optimum sıralamayı bulan ek bir bölüm ekledik. Eklediğimiz bu kısım bazı devrelerin maliyetini azaltırken, programın çalışma süresini artırmıştır. İkinci aşama, oluşturduğumuz şablonları kullanarak, sentezlenen devrelerde optimizasyon yapmaktadır. Şablonlar, aynı fonksiyonu daha az sayıda kapıyla gerçekleyen ve devredeki eşdeğeri ile değiştirilerek toplam kapı sayısında düşüş sağlayan devrelerdir. Şablonlarımızı iki farklı yolla oluşturduk. Birincisi, tersinir kapı kütüphanemizi kullanarak. İkincisi de bu kütüphanedeki kapıların içlerinde bulunan kuantum kapıları göz önüne alarak. Birinci yöntem, sıralama algoritmasının uygulanmasından sonra, aynı iki kapının yanyana gelebileceği göz önünde bulundurularak üretilmiştir. İkinci türdeki şablonlarda, sentezlediğimiz devrelerde sıkça kullandığımız Toffoli kapısının, kuantum kapılarla (V, V† ve CNOT) kaç farklı şekilde gerçekleştirilebileceğini inceledik. Bu aşamada, kompleks sayılardan oluşan matrisleri kullanacağımız için, MATLAB programını kullandık. Devre içiersinde Toffoli kapısının yanına gelen CNOT kapılarından bir kısmının optimizasyon için kullanılabileceğini gösterdik. Ayrıca çalışmamızda, pozitif kontrollü kapılara (CNT) ek olarak negatif kontrollülerinde sentezleme aşamasına eklenmesiyle devre maliyetlerinde önemli ölçüde iyileştirmeler elde ettik. Kuantum hesaplama, deneysel olarak bir çok farklı şekilde gerçekleştirilmiştir. Her gerçeklemenin, kendine özgü prensipleri ve özellikleri olduğundan, algoritmalardaki kapıların uygulanış biçimi de farklı olmaktadır. Bu nedenle, her yöntem için ayrı kapı maliyetleri oluşmaktır. Çalışmamızki kuantum devrelerin maliyetlerini literatürde yaygın olarak kullanılan NCV-111 maliyet metriğini kullanarak hesapladık. Son olarak, yöntemimizi literatürde bulunan çalışmalar ile kıyasladık.This thesis presents a new approach for the synthesis of quantum circuits. Quantum computers, more specifically quantum algorithims, take on the eyes with their computational promises. They paved the way for calculation of the complex problems that can't be solved in polynomial time by traditional counterparts. Exploiting quantum mechanical phenomena and its features is the main power source of the quantum computing idea. This is also leaning on the concept that accepts information as a physical item. In addition, quantum mechanical unitarity brings reversibility for quantum algorithms and quantum circuits. This creates ideal application area for reversible computing and reversible circuit design. Reversible computing is motivating scientist and researchers for years to achieve energy efficient computation. With the help of advancing technology, quantum computation become applicable. At this point, reversible quantum circuit design is coming forward that is the core of this computation. When compared with classical computation methods, quantum systems are very sensitive. This is one of the main reasons to synthesize these circuits minimally as possible. Depending on quantum computation method, each gate in quantum circuits corresponding to one or more pulse operations. Therefore, optimized circuits will improve both the security and the run time of the computation. Still, optimal circuit synthesis for higher bit count is hard to achieve, it can take very long time which is not practical at all. To compete with classical computation in a realistic manner, this is one of the main obstacles to overcome and it constitutes the main motivation why we aim at a fast synthesis algorithm in this thesis. To fulfill the needs of this upcoming technology, we perform synthesis and optimization of quantum circuits in two main parts. In the first part, we propose a fast synthesis algorithm that implements any given reversible Boolean function with quantum gates. Instead of an exhaustive search on every given function, our algorithm creates a library of essential functions and performs sorting to obtain desired function. In the second part, we optimize our circuits by using templates. The proposed templates mainly consist of identical neighbor gates and Toffoli gates, realized with V, V† and CNOT gates. We also improve the CNT library by taking negative control lines into account which provides important circuit cost reduction. We call this new library as PN-CNT that stands for “Positively and Negatively Controlled CNOT, Not, Toffoli”. Quantum computers implemented in various ways so far. Each implementation has its own physical cost. For the calculation of quantum circuit cost, we preferred to use widely accepted NCV-111 cost metric in this thesis. Finally we compared our results with studies in the literature.Yüksek Lisan

Reversible Computation: Extending Horizons of Computing

This open access State-of-the-Art Survey presents the main recent scientific outcomes in the area of reversible computation, focusing on those that have emerged during COST Action IC1405 "Reversible Computation - Extending Horizons of Computing", a European research network that operated from May 2015 to April 2019. Reversible computation is a new paradigm that extends the traditional forwards-only mode of computation with the ability to execute in reverse, so that computation can run backwards as easily and naturally as forwards. It aims to deliver novel computing devices and software, and to enhance existing systems by equipping them with reversibility. There are many potential applications of reversible computation, including languages and software tools for reliable and recovery-oriented distributed systems and revolutionary reversible logic gates and circuits, but they can only be realized and have lasting effect if conceptual and firm theoretical foundations are established first

New Data Structures and Algorithms for Logic Synthesis and Verification

The strong interaction between Electronic Design Automation (EDA) tools and Complementary Metal-Oxide Semiconductor (CMOS) technology contributed substantially to the advancement of modern digital electronics. The continuous downscaling of CMOS Field Effect Transistor (FET) dimensions enabled the semiconductor industry to fabricate digital systems with higher circuit density at reduced costs. To keep pace with technology, EDA tools are challenged to handle both digital designs with growing functionality and device models of increasing complexity. Nevertheless, whereas the downscaling of CMOS technology is requiring more complex physical design models, the logic abstraction of a transistor as a switch has not changed even with the introduction of 3D FinFET technology. As a consequence, modern EDA tools are fine tuned for CMOS technology and the underlying design methodologies are based on CMOS logic primitives, i.e., negative unate logic functions. While it is clear that CMOS logic primitives will be the ultimate building blocks for digital systems in the next ten years, no evidence is provided that CMOS logic primitives are also the optimal basis for EDA software. In EDA, the efficiency of methods and tools is measured by different metrics such as (i) the result quality, for example the performance of a digital circuit, (ii) the runtime and (iii) the memory footprint on the host computer. With the aim to optimize these metrics, the accordance to a specific logic model is no longer important. Indeed, the key to the success of an EDA technique is the expressive power of the logic primitives handling and solving the problem, which determines the capability to reach better metrics. In this thesis, we investigate new logic primitives for electronic design automation tools. We improve the efficiency of logic representation, manipulation and optimization tasks by taking advantage of majority and biconditional logic primitives. We develop synthesis tools exploiting the majority and biconditional expressiveness. Our tools show strong results as compared to state-of-the-art academic and commercial synthesis tools. Indeed, we produce the best results for several public benchmarks. On top of the enhanced synthesis power, our methods are the natural and native logic abstraction for circuit design in emerging nanotechnologies, where majority and biconditional logic are the primitive gates for physical implementation. We accelerate formal methods by (i) studying properties of logic circuits and (ii) developing new frameworks for logic reasoning engines. We prove non-trivial dualities for the property checking problem in logic circuits. Our findings enable sensible speed-ups in solving circuit satisfiability. We develop an alternative Boolean satisfiability framework based on majority functions. We prove that the general problem is still intractable but we show practical restrictions that can be solved efficiently. Finally, we focus on reversible logic where we propose a new equivalence checking approach. We exploit the invertibility of computation and the functionality of reversible gates in the formulation of the problem. This enables one order of magnitude speed up, as compared to the state-of-the-art solution. We argue that new approaches to solve EDA problems are necessary, as we have reached a point of technology where keeping pace with design goals is tougher than ever

Reversible Computation: Extending Horizons of Computing

This open access State-of-the-Art Survey presents the main recent scientific outcomes in the area of reversible computation, focusing on those that have emerged during COST Action IC1405 "Reversible Computation - Extending Horizons of Computing", a European research network that operated from May 2015 to April 2019. Reversible computation is a new paradigm that extends the traditional forwards-only mode of computation with the ability to execute in reverse, so that computation can run backwards as easily and naturally as forwards. It aims to deliver novel computing devices and software, and to enhance existing systems by equipping them with reversibility. There are many potential applications of reversible computation, including languages and software tools for reliable and recovery-oriented distributed systems and revolutionary reversible logic gates and circuits, but they can only be realized and have lasting effect if conceptual and firm theoretical foundations are established first

New Logic Synthesis As Nanotechnology Enabler (invited paper)

Nanoelectronics comprises a variety of devices whose electrical properties are more complex as compared to CMOS, thus enabling new computational paradigms. The potentially large space for innovation has to be explored in the search for technologies that can support large-scale and high- performance circuit design. Within this space, we analyze a set of emerging technologies characterized by a similar computational abstraction at the design level, i.e., a binary comparator or a majority voter. We demonstrate that new logic synthesis techniques, natively supporting this abstraction, are the technology enablers. We describe models and data-structures for logic design using emerging technologies and we show results of applying new synthesis algorithms and tools. We conclude that new logic synthesis methods are required to both evaluate emerging technologies and to achieve the best results in terms of area, power and performance

Formal Methods in Quantum Circuit Design

The design and compilation of correct, efficient quantum circuits is integral to the future operation of quantum computers. This thesis makes contributions to the problems of optimizing and verifying quantum circuits, with an emphasis on the development of formal models for such purposes. We also present software implementations of these methods, which together form a full stack of tools for the design of optimized, formally verified quantum oracles. On the optimization side, we study methods for the optimization of Rz and CNOT gates in Clifford+Rz circuits. We develop a general, efficient optimization algorithm called phase folding, which reduces the number of Rz gates without increasing any metrics by computing its phase polynomial. This algorithm can further be combined with synthesis techniques for CNOT-dihedral operators to optimize circuits with respect to particular costs. We then study the optimal synthesis problem for CNOT-dihedral operators from the perspectives of Rz and CNOT gate optimization. In the case of Rz gate optimization, we show that the optimal synthesis problem is polynomial-time equivalent to minimum-distance decoding in certain Reed-Muller codes. For the CNOT optimization problem, we show that the optimal synthesis problem is at least as hard as a combinatorial problem related to Gray codes. In both cases, we develop heuristics for the optimal synthesis problem, which together with phase folding reduces T counts by 42% and CNOT counts by 22% across a suite of real-world benchmarks. From the perspective of formal verification, we make two contributions. The first is the development of a formal model of quantum circuits with ancillary bits based on the Feynman path integral, along with a concrete verification algorithm. The path integral model, with some syntactic sugar, further doubles as a natural specification language for quantum computations. Our experiments show some practical circuits with up to hundreds of qubits can be efficiently verified. Our second contribution is a formally verified, optimizing compiler for reversible circuits. The compiler compiles a classical, irreversible language to reversible circuits, with a formal, machine-checked proof of correctness written in the proof assistant F*. The compiler is structured as a partial evaluator, allowing verification to be carried out significantly faster than previous results