Novel Rail Clamp Architectures and Their Systematic Design

abstract: Rail clamp circuits are widely used for electrostatic discharge (ESD) protection in semiconductor products today. A step-by-step design procedure for the traditional RC and single-inverter-based rail clamp circuit and the design, simulation, implementation, and operation of two novel rail clamp circuits are described for use in the ESD protection of complementary metal-oxide-semiconductor (CMOS) circuits. The step-by-step design procedure for the traditional circuit is technology-node independent, can be fully automated, and aims to achieve a minimal area design that meets specified leakage and ESD specifications under all valid process, voltage, and temperature (PVT) conditions. The first novel rail clamp circuit presented employs a comparator inside the traditional circuit to reduce the value of the time constant needed. The second circuit uses a dynamic time constant approach in which the value of the time constant is dynamically adjusted after the clamp is triggered. Important metrics for the two new circuits such as ESD performance, latch-on immunity, clamp recovery time, supply noise immunity, fastest power-on time supported, and area are evaluated over an industry-standard PVT space using SPICE simulations and measurements on a fabricated 40 nm test chip.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201

Design of reliable and energy-efficient high-speed interface circuits

The data-rate demand in high-speed interface circuits increases exponentially every year. High-speed I/Os are better implemented in advanced process technologies for lower-power systems, with the advantages of improved driving capability of the transistors and reduced parasitic capacitance. However, advanced technologies are not necessarily advantageous in terms of device reliability; in particular device failure from electrostatic discharge (ESD) becomes more likely in nano-scale process nodes. In order to secure ESD resiliency, the size of ESD devices on I/O pads should be sufficiently large, which may potentially reduce I/O speed. These two conflicting requirements in high-speed I/O design sometimes require sacrifice to one of the two properties. In this dissertation, three different approaches are proposed to achieve reliable and energy-efficient interface circuits. As the first approach, a novel ESD self-protection scheme to utilize “adaptive active bias conditioning” is proposed to reduce voltage stress on the vulnerable transistors, thereby reducing the burden on ESD protection devices. The second approach is to cancel out effective parasitic capacitance from ESD devices by the T-coil network. Voltage overshoot generated by magnetic coupling of the T-coil network can be suppressed by the proposed “inductance halving” technique, which reduces mutual inductance during ESD. The last approach employs system-level knowledge in the design of an ADC-based receiver for high intersymbol interference (ISI) channels. As a system-level performance metric, bit-error rate (BER) is adopted to mitigate a bit-resolution requirement in “BER-optimal ADC”, which can lead to 2× power-efficiency in the flash ADC and achieve a better BER performance

A Systematical Approach For A Robust Electrostatic Discharge (Esd) Design

Dengan peningkatan kegagalan cip disebabkan ESD, reka bentuk IC untuk membangunkan aliran reka bentuk ESD yang komprehensif menggunakan pelbagai perisian automatik yang boleh mengesan secara berkesan kelemahan reka bentuk ESD lebih awal dalam fasa reka bentuk telah menjadi semakin penting. Kita perlu mendapatkan reka bentuk (reka bentuk ESD dalam konteks ini) yang tepat pada kali pertama. Aliran pengesahan reka bentuk ESD sedia ada adalah sama ada bergantung susun atur (pemeriksa peraturan reka bentuk susun atur), bergantung litar (simulasi litar) atau terlalu lewat untuk memintas masalah reka bentuk ESD. Satu cadangan aliran reka bentuk ESD ditunjukkan dengan beberapa idea reka bentuk ESD yang betul-masa-pembinaan. Satu metodologi reka bentuk dan strategi perlindungan ESD untuk sistem digital, teguh kepada peristiwa-peristiwa ESD, dibangunkan dan disahkan untuk teknologi MOS komersial 45nm, 65 nm dan 90 nm. Aliran reka bentuk ESD pada dasarnya mengambil berat tentang model tekanan ESD HBM, MM dan CDM. Aliran reka bentuk ESD yang dihasilkan menunjukkan pelbagai jenis kesilapan reka bentuk telah dapat dikesan dan mewajarkan keperluan untuk peningkatan strategi perlindungan ESD ini. Kita mempunyai pemeriksa aturan reka bentuk bentangan, simulasi litar, alat automatik letakan pengapit dan beberapa alatan lain dalam aliran reka bentuk ESD ini. Menggunakan teknik-teknik pengukuran, pemodelan dan simulasi, metodologi reka bentuk dan strategi perlindungan ESD telah berjaya diimplementasikan ke dalam aliran reka bentuk utama komersial. Cip-cip ujian tertentu, direkabentuk menggunakan aturan-aturan ESD konvensional yang disasarkan untuk perlindungan tekanan ESD, telah digunakan sebagai bahan-bahan ujian bagi metodologi baru ini. Perubahan reka bentuk ini menghasilkan cip yang melepasi aras-aras tekanan ESD ( piawaian industri HBM 2.5kV, MM 200V dan CDM 500V) dengan hampir tiada pindaan reka bentuk yang besar. ________________________________________________________________________________________________________________________ With the increase events of ESD-induced chip failure, it has become vital for the IC design community to develop a comprehensive ESD design flow with various automated tools that can efficiently detect ESD design weakness early in the design phase. We need to get the design (ESD design in this context) right at the very first time. Existing ESD design verification flow is either layout dependent (layout design rule checker), circuit dependent (circuit simulation) or too late to intercept the ESD design problem. A proposed ESD design flow is demonstrated with some correct-by-construction ESD design idea. An ESD design methodology and protection strategy for digital systems, robust to ESD events, is developed and validated for commercial 45nm, 65 nm and 90 nm MOS technologies. The ESD design flow basically takes care of the HBM, MM and CDM ESD stress models. The ESD design flow demonstrates different type of design errors that the tools have uncovered and justify the need for this enhanced ESD protection strategy. We have layout design rule checker, circuit simulation, auto clamp placement tool and other tools in our ESD design flow. Using these measurement, modeling and simulation techniques, the design methodology and protection strategy was successfully implemented into a commercial mainstream design flow. Specific IC test chips, designed using conventional ESD rules targeted for ESD stress protection, were used as test vehicles for the new methodology; resulting design changes resulted in chips that passed levels of ESD stress ( industrial standard of HBM 2.5kV, MM 200V and CDM 500V) with virtually no major design amendments

Uncalibrated TCAD methodology for analysis of ESD protection devices

In this work, an uncalibrated TCAD methodology for simulation of electrostatic discharge (ESD) devices is presented. The methodology addresses TCAD setup issues including device construction, boundary conditions, and choosing a physical model and parameters. A major trade-off between computation complexity and accuracy, 2D vs. 3D simulations, is examined in detail. TCAD simulation results for the GGNMOS in 32 nm CMOS technology is compared with published measurement results for methodology validation. The established TCAD methodology is then applied to ESD protection silicon controlled rectifier (SCR) devices to identify physical causes for high overshoot of a certain SCR layout, and to verify proposed improvements. The performance of the SCR with the improved layout structure is characterized in silicon to prove its consistency with TCAD prediction

On-Chip ESD Protection Design: Optimized Clamps

The extensive use of Integrated Circuits (ICs) means complex working conditions for these tiny chips. To guarantee the ICs could work properly in various environments, some special protection strategies are required to improve the reliability of system. From all the possible reliability issues, the electrostatics discharge (ESD) might be the most common one. The peak current of electrostatics can be as high as tens of amperes and the peak voltage can be over thousand voltages. In contrast, the size of semiconductor device fabricated is continuing to scale down, making it even more vulnerable to high level overstress and current surge induced by ESD event. To protect the on-chip semiconductor from damage, some extra clamp cells are put together to consist a network. The network can redirect the superfluous current through the ESD network and clamp the voltage to a low level. In this dissertation, one design concept is introduced that uses the combination of some basic ESD devices to meet different requirements first, and then tries to establish parasitic current path among these devices to further increase the current handling capability. Some design cases are addressed to demonstrate this design concept is valid and efficient: 1. A combination of silicon-controlled-rectifier (SCR) and diode cluster is implemented to resolve the overshoot issue under fast ESD event. 2. A new SCR structure is introduced, which can be used as padding device to increase the clamping voltage without affecting other parameters. Based on this padding device, two design cases are introduced. 3. A controllable SCR clamp structure is presented, which has high current handling capability and can be controlled with by small signal. All these structures and topologies described in this dissertation are compatible with most of popular semiconductor fabrication process

Analysis of design strategies for RF ESD problems in CMOS circuits

This thesis analyses the design strategies used to protect RF circuits that are implemented in CMOS technologies. It investigates, in detail, the physical mechanisms involved when a ggNMOS structure is exposed to an ESD event and undergoes snapback. The understanding gained is used to understand why the performance of the current RF ESD clamp is poor and suggestions are made as to how the performance of ggNMOS clamps can be improved beyond the current body of knowledge. The ultimate aim is to be able to design effective ESD protection clamps whilst minimising the effect the circuit has on RF I/O signals. A current ggNMOS based RF ESD I/O protection circuit is analysed in detail using a Transmission Line Pulse (TLP) tester. This is shown to be a very effective diagnostic tool by showing many characteristics of the ggNMOS during the triggering and conducting phase of the ESD event and demonstrate deficiencies in the clamp design. The use of a FIB enhances the analysis by allowing the isolation of individual components in the circuit and therefore their analysis using the TLP tester. SPICE simulations are used to provide further commentary on the debate surrounding the specification required of a TLP tester for there to be a good correlation between a TLP test and the industry standard Human Body Model (HBM) ESD test. Finite element simulations are used to probe deeper in to the mechanisms involved when a ggNMOS undergoes snapback especially with regard to the contribution parasitic components within the ggNMOS make to the snapback process. New ggNMOS clamps are proposed which after some modification are shown to work. Some of the finite element experiments are repeated in a 0.18μπ7. process CMOS test chip and a comparison is made between the two sets of results. In the concluding chapter understanding that has been gained from previous chapters is combined with the published body of knowledge to suggest and explain improvements in the design of a ggNMOS for RF and standard applications. These improvements will improve homogeneity of ggNMOS operation thus allowing the device size to be reduced and parasitic loading for a given ESD performance. These techniques can also be used to ensure that the ESD current does not take an unintended path through the chip

Electrostatic Discharge

As we enter the nanoelectronics era, electrostatic discharge (ESD) phenomena is an important issue for everything from micro-electronics to nanostructures. This book provides insight into the operation and design of micro-gaps and nanogenerators with chapters on low capacitance ESD design in advanced technologies, electrical breakdown in micro-gaps, nanogenerators from ESD, and theoretical prediction and optimization of triboelectric nanogenerators. The information contained herein will prove useful for for engineers and scientists that have an interest in ESD physics and design

Study Of Esd Effects On Rf Power Amplifiers

Today, ESD is a major consideration in the design and manufacture of ICs. ESD problems are increasing in the electronics industry because of the increasing trend toward higher speed and smaller device sizes. There is growing interest in knowing the effects of ESD protection circuit on the performance of semiconductor integrated circuits (ICs) because of the impact it has on core RF circuit performance. This study investigated the impact of ESD protection circuit on RF Power amplifiers. Even though ESD protection for digital circuits has been known for a while, RF-ESD is a challenge. From a thorough literature search on prior art ESD protection circuits, Silicon controlled rectifier was found to be most effective and reliable ESD protection for power amplifier circuit. A SCR based ESD protection was used to protect the power amplifier and a model was developed to gain better understanding of ESD protected power amplifiers. Simulated results were compared and contrasted against theoretically derived equations. A 5.2GHz fully ESD protected Class AB power amplifier was designed and simulated using TSMC 0.18 um technology. Further, the ESD protection circuit was added to a cascoded Class-E power amplifier operating at 5.2 GHz. ADS simulation results were used to analyze the PA’s RF performance degradation. Various optimization techniques were used to improve the RF circuit performance

Development of the readout electronics for the high luminosity upgrade of the CMS outer strip tracker

The High-luminosity upgrade of the LHC will deliver the dramatic increase in luminosity required for precision measurements and to probe Beyond the Standard Model theories. At the same time, it will present unprecedented challenges in terms of pileup and radiation degradation. The CMS experiment is set for an extensive upgrade campaign, which includes the replacement of the current Tracker with another all-silicon detector with improved performance and reduced mass. One of the most ambitious aspects of the future Tracker will be the ability to identify high transverse momentum track candidates at every bunch crossing and with very low latency, in order to include tracking information at the L1 hardware trigger stage, a critical and effective step to achieve triggers with high purity and low threshold. This thesis presents the development and the testing of the CMS Binary Chip 2 (CBC2), a prototype Application Specific Integrated Circuit (ASIC) for the binary front-end readout of silicon strip detectors modules in the Outer Tracker, which also integrates the logic necessary to identify high transverse momentum candidates by correlating hits from two silicon strip detectors, separated by a few millimetres. The design exploits the relation between the transverse momentum and the curvature in the trajectory of charged particles subject to the large magnetic field of CMS. The logic which follows the analogue amplification and binary conversion rejects clusters wider than a programmable maximum number of adjacent strips, compensates for the geometrical offset in the alignment of the module, and correlates the hits between the two sensor layers. Data are stored in a memory buffer before being transferred to an additional buffer stage and being serially read-out upon receipt of a Level 1 trigger. The CBC2 has been subject to extensive testing since its production in January 2013: this work reports the results of electrical characterization, of the total ionizing dose irradiation tests, and the performance of a prototype module instrumented with CBC2 in realistic conditions in a beam test. The latter is the first experimental demonstration of the Pt-selection principle central to the future of CMS. Several total-ionizing-dose tests highlighted no functional issue, but observed significant excess static current for doses <1 Mrad. The source of the excess was traced to static leakage current in the memory pipeline, and is believed to be a consequence of the high instantaneous dose delivered by the x-ray setup. Nevertheless, a new SRAM layout aimed at removing the leakage path was proposed for the CBC3. The results of single event upset testing of the chip are also reported, two of the three distinct memory circuits used in the chip were proven to meet the expected robustness, while the third will be replaced in the next iteration of the chip. Finally, the next version of the ASIC is presented, highlighting the additional features of the final prototype, such as half-strip resolution, additional trigger logic functionality, longer trigger latency and higher rate, and fully synchronous stub readout.Open Acces