Novel Materials and Devices for Terahertz Detection and Emission for Sensing, Imaging and Communication

Technical advancement is required to attain a high data transmission rate, which entails expanding beyond the currently available bandwidth and establishing a new standard for the highest data rates, which mandates a higher frequency range and larger bandwidth. The THz spectrum (0.1-10 THz) has been considered as an emerging next frontier for the future 5G and beyond technology. THz frequencies also offer unique characteristics, such as penetrating most dielectric materials like fabric, plastic, and leather, making them appealing for imaging and sensing applications. Therefore, employing a high-power room temperature, tunable THz emitters, and a high responsivity THz detector is essential. Dyakonov-theory Shur\u27s was applied in this dissertation to achieve tunable THz detection and emission by plasma waves in high carrier density channels of field-effect devices. The first major contribution of this dissertation is developing graphene-based THz plasmonics detector with high responsivity. An upside-down free-standing graphene in a field effect transistor based resonant room temperature THz detector device with significantly improved mobility and gate control has been presented. The highest achieved responsivity is ~3.1kV/W, which is more than 10 times higher than any THz detector reported till now. The active region is predominantly single-layer graphene with multi-grains, even though the fabricated graphene THz detector has the highest responsivity. The challenges encountered during the fabrication and measurement of the graphene-based detector have been described, along with a strategy to overcome them while preserving high graphene mobility. In our new design, a monolayer of hBN underneath the graphene layer has been deposited to increase the mobility and electron concentration rate further. We also investigated the diamond-based FETs for their potential characteristics as a THz emitters and detectors. Diamond\u27s wide bandgap, high breakdown field, and high thermal conductivity attributes make it a potential semiconductor material for high voltage, high power, and high-temperature operation. Diamond is a good choice for THz and sub-THz applications because of its high optical phonon scattering and high momentum relaxation time. Numerical and analytical studies of diamond materials, including p-diamond and n-diamond materials, are presented, indicating their effectiveness as a prospective contender for high temperature and high power-based terahertz applications These detectors are expected to be a strong competitor for future THz on-chip applications due to their high sensitivity, low noise, tunability, compact size, mobility, faster response time, room temperature operation, and lower cost. Furthermore, when plasma wave instabilities are induced with the proper biasing, the same devices can be employed as THz emitters, which are expected to have a higher emission power. Another key contribution is developing a method for detecting counterfeit, damaged, forged, or defective ICs has been devised utilizing a new non-destructive and unobtrusive terahertz testing approach to address the crucial point of hardware cybersecurity and system reliability. The response of MMICs, VLSI, and ULSIC to incident terahertz and sub-terahertz radiation at the circuit pins are measured and analyzed using deep learning. More sophisticated terahertz response profiles and signatures of specific ICs can be created by measuring a more significant number of pins under different frequencies, polarizations, and depth of focus. The proposed method has no effect on ICs operation and could provide precise ICs signatures. The classification process between the secure and unsecure ICs images has been explained using data augmentation and transfer learning-based convolution neural network with ~98% accuracy. A planar nanomatryoshka type core-shell resonator with hybrid toroidal moments is shown both experimentally and analytically, allowing unique characteristics to be explored. This resonator may be utilized for accurate sensing, immunobiosensing, quick switching, narrow-band filters, and other applications

Design and Control of Electrical Motor Drives

Dear Colleagues, I am very happy to have this Special Issue of the journal Energies on the topic of Design and Control of Electrical Motor Drives published. Electrical motor drives are widely used in the industry, automation, transportation, and home appliances. Indeed, rolling mills, machine tools, high-speed trains, subway systems, elevators, electric vehicles, air conditioners, all depend on electrical motor drives.However, the production of effective and practical motors and drives requires flexibility in the regulation of current, torque, flux, acceleration, position, and speed. Without proper modeling, drive, and control, these motor drive systems cannot function effectively.To address these issues, we need to focus on the design, modeling, drive, and control of different types of motors, such as induction motors, permanent magnet synchronous motors, brushless DC motors, DC motors, synchronous reluctance motors, switched reluctance motors, flux-switching motors, linear motors, and step motors.Therefore, relevant research topics in this field of study include modeling electrical motor drives, both in transient and in steady-state, and designing control methods based on novel control strategies (e.g., PI controllers, fuzzy logic controllers, neural network controllers, predictive controllers, adaptive controllers, nonlinear controllers, etc.), with particular attention to transient responses, load disturbances, fault tolerance, and multi-motor drive techniques. This Special Issue include original contributions regarding recent developments and ideas in motor design, motor drive, and motor control. The topics include motor design, field-oriented control, torque control, reliability improvement, advanced controllers for motor drive systems, DSP-based sensorless motor drive systems, high-performance motor drive systems, high-efficiency motor drive systems, and practical applications of motor drive systems. I want to sincerely thank authors, reviewers, and staff members for their time and efforts. Prof. Dr. Tian-Hua Liu Guest Edito

Electrostatic Discharge

As we enter the nanoelectronics era, electrostatic discharge (ESD) phenomena is an important issue for everything from micro-electronics to nanostructures. This book provides insight into the operation and design of micro-gaps and nanogenerators with chapters on low capacitance ESD design in advanced technologies, electrical breakdown in micro-gaps, nanogenerators from ESD, and theoretical prediction and optimization of triboelectric nanogenerators. The information contained herein will prove useful for for engineers and scientists that have an interest in ESD physics and design

THz detection and amplification using plasmonic Field Effect Transistors driven by DC drain currents

We report on the numerical and theoretical results of sub-THz and THz detection by a current-driven InGaAs/GaAs plasmonic Field-Effect Transistor (TeraFET). New equations are developed to account for the channel length dependence of the drain voltage and saturation current. Numerical simulation results demonstrate that the effect of drain bias current on the source-to-drain response voltage (dU) varies with the device channel length. In a long-channel TeraFET where plasmonic oscillations cannot reach the drain, dU is always positive and rises rapidly with increasing drain current. For a short device in which plasmonic oscillations reach the drain, the current-induced nonuniform electric field leads to a negative response, agreeing with previous observations. At negative dU, the amplitude of the small-signal voltage at the drain side becomes larger than that at the source side. Thus, the device effectively serves as a THz amplifier in this condition. Under the resonant mode, the negative response can be further amplified near the resonant peaks. A new expression of dU is proposed to account for this resonant effect. Based on those expressions, a current-driven TeraFET spectrometer is proposed. The ease of implementation and simplified calibration procedures make it competitive or superior compared with other TeraFET-based spectrometers.Comment: 23 pages, 11 figures, 1 tabl

Process-induced Structural Variability-aware Performance Optimization for Advanced Nanoscale Technologies

Department of Electrical EngineeringAs the CMOS technologies reach the nanometer regime through aggressive scaling, integrated circuits (ICs) encounter scaling impediments such as short channel effects (SCE) caused by reduced ability of gate control on the channel and line-edge roughness (LER) caused by limits of the photolithography technologies, leading to serious device parameter fluctuations and makes the circuit analysis difficult. In order to overcome scaling issues, multi-gate structures are introduced from the planar MOSFET to increase the gate controllability. The goal of this dissertation is to analyze structural variations induced by manufacturing process in advanced nanoscale devices and to optimize its impacts in terms of the circuit performances. If the structural variability occurs, aside from the endeavor to reduce the variability, the impact must be taken into account at the design level. Current compact model does not have device structural variation model and cannot capture the impact on the performance/power of the circuit. In this research, the impacts of structural variation in advanced nanoscale technology on the circuit level parameters are evaluated and utilized to find the optimal device shape and structure through technology computer-aided-design (TCAD) simulations. The detail description of this dissertation is as follows: Structural variation for nanoscale CMOS devices is investigated to extend the analysis approach to multi-gate devices. Simple and accurate modeling that analyzes non-rectilinear gate (NRG) CMOS transistors with a simplified trapezoidal approximation method is proposed. The electrical characteristics of the NRG gate, caused by LER, are approximated by a trapezoidal shape. The approximation is acquired by the length of the longest slice, the length of the smallest slice, and the weighting factor, instead of taking the summation of all the slices into account. The accuracy can even be improved by adopting the width-location-dependent factor (Weff). The positive effect of diffusion rounding at the transistor source side of CMOS is then discussed. The proposed simple layout method provides boosting the driving strength of logic gates and also saving the leakage power with a minimal area overhead. The method provides up to 13% speed up and also saves up to 10% leakage current in an inverter simulation by exploiting the diffusion rounding phenomena in the transistors. The performance impacts of the trapezoidal fin shape of a double-gate FinFET are then discussed. The impacts are analyzed with TCAD simulations and optimal trapezoidal angle range is proposed. Several performance metrics are evaluated to investigate the impact of the trapezoidal fin shape on the circuit operation. The simulations show that the driving capability improves, and the gate capacitance increases as the bottom fin width of the trapezoidal fin increases. The fan-out 4 (FO4) inverter and ring-oscillator (RO) delay results indicate that careful optimization of the trapezoidal angle can increase the speed of the circuit because the ratios of the current and capacitance have different impacts depending on the trapezoidal angle. Last but not least, the electrical characteristics of a double-gate-all-around (DGAA) transistor with an asymmetric channel width using device simulations are also investigated in this work. The DGAA FET, a kind of nanotube field-effect transistor (NTFET), can solve the problem of loss of gate controllability of the channel and provide improved short-channel behavior. Simulation results reveal that, according to the carrier types, the location of the asymmetry has a different effect on the electrical properties of the devices. Thus, this work proposes the n/p DGAA FET structure with an asymmetric channel width to form the optimal inverter. Various electrical metrics are analyzed to investigate the benefits of the optimal inverter structure over the conventional GAA inverter structure. In the optimum structure, 27% propagation delay and 15% leakage power improvement can be achieved. Analysis and optimization for device-level variability are critical in integrated circuit designs of advanced technology nodes. Thus, the proposed methods in this dissertation will be helpful for understanding the relationship between device variability and circuit performance. The research for advanced nanoscale technologies through intensive TCAD simulations, such as FinFET and GAA, suggests the optimal device shape and structure. The results provide a possible solution to design high performance and low power circuits with minimal design overhead.ope

Wide Bandgap Based Devices

Emerging wide bandgap (WBG) semiconductors hold the potential to advance the global industry in the same way that, more than 50 years ago, the invention of the silicon (Si) chip enabled the modern computer era. SiC- and GaN-based devices are starting to become more commercially available. Smaller, faster, and more efficient than their counterpart Si-based components, these WBG devices also offer greater expected reliability in tougher operating conditions. Furthermore, in this frame, a new class of microelectronic-grade semiconducting materials that have an even larger bandgap than the previously established wide bandgap semiconductors, such as GaN and SiC, have been created, and are thus referred to as “ultra-wide bandgap” materials. These materials, which include AlGaN, AlN, diamond, Ga2O3, and BN, offer theoretically superior properties, including a higher critical breakdown field, higher temperature operation, and potentially higher radiation tolerance. These attributes, in turn, make it possible to use revolutionary new devices for extreme environments, such as high-efficiency power transistors, because of the improved Baliga figure of merit, ultra-high voltage pulsed power switches, high-efficiency UV-LEDs, and electronics. This Special Issue aims to collect high quality research papers, short communications, and review articles that focus on wide bandgap device design, fabrication, and advanced characterization. The Special Issue will also publish selected papers from the 43rd Workshop on Compound Semiconductor Devices and Integrated Circuits, held in France (WOCSDICE 2019), which brings together scientists and engineers working in the area of III–V, and other compound semiconductor devices and integrated circuits

Magnetic Material Modelling of Electrical Machines

The need for electromechanical energy conversion that takes place in electric motors, generators, and actuators is an important aspect associated with current development. The efficiency and effectiveness of the conversion process depends on both the design of the devices and the materials used in those devices. In this context, this book addresses important aspects of electrical machines, namely their materials, design, and optimization. It is essential for the design process of electrical machines to be carried out through extensive numerical field computations. Thus, the reprint also focuses on the accuracy of these computations, as well as the quality of the material models that are adopted. Another aspect of interest is the modeling of properties such as hysteresis, alternating and rotating losses and demagnetization. In addition, the characterization of materials and their dependence on mechanical quantities such as stresses and temperature are also considered. The reprint also addresses another aspect that needs to be considered for the development of the optimal global system in some applications, which is the case of drives that are associated with electrical machines

Potential and Challenges of Analog Reconfigurable Computation in Modern and Future CMOS

In this work, the feasibility of the floating-gate technology in analog computing platforms in a scaled down general-purpose CMOS technology is considered. When the technology is scaled down the performance of analog circuits tends to get worse because the process parameters are optimized for digital transistors and the scaling involves the reduction of supply voltages. Generally, the challenge in analog circuit design is that all salient design metrics such as power, area, bandwidth and accuracy are interrelated. Furthermore, poor flexibility, i.e. lack of reconfigurability, the reuse of IP etc., can be considered the most severe weakness of analog hardware. On this account, digital calibration schemes are often required for improved performance or yield enhancement, whereas high flexibility/reconfigurability can not be easily achieved. Here, it is discussed whether it is possible to work around these obstacles by using floating-gate transistors (FGTs), and analyze problems associated with the practical implementation. FGT technology is attractive because it is electrically programmable and also features a charge-based built-in non-volatile memory. Apart from being ideal for canceling the circuit non-idealities due to process variations, the FGTs can also be used as computational or adaptive elements in analog circuits. The nominal gate oxide thickness in the deep sub-micron (DSM) processes is too thin to support robust charge retention and consequently the FGT becomes leaky. In principle, non-leaky FGTs can be implemented in a scaled down process without any special masks by using “double”-oxide transistors intended for providing devices that operate with higher supply voltages than general purpose devices. However, in practice the technology scaling poses several challenges which are addressed in this thesis. To provide a sufficiently wide-ranging survey, six prototype chips with varying complexity were implemented in four different DSM process nodes and investigated from this perspective. The focus is on non-leaky FGTs, but the presented autozeroing floating-gate amplifier (AFGA) demonstrates that leaky FGTs may also find a use. The simplest test structures contain only a few transistors, whereas the most complex experimental chip is an implementation of a spiking neural network (SNN) which comprises thousands of active and passive devices. More precisely, it is a fully connected (256 FGT synapses) two-layer spiking neural network (SNN), where the adaptive properties of FGT are taken advantage of. A compact realization of Spike Timing Dependent Plasticity (STDP) within the SNN is one of the key contributions of this thesis. Finally, the considerations in this thesis extend beyond CMOS to emerging nanodevices. To this end, one promising emerging nanoscale circuit element - memristor - is reviewed and its applicability for analog processing is considered. Furthermore, it is discussed how the FGT technology can be used to prototype computation paradigms compatible with these emerging two-terminal nanoscale devices in a mature and widely available CMOS technology.Siirretty Doriast