RF MEMS/NEMS RESONATORS FOR WIRELESS COMMUNICATION SYSTEMS AND ADSORPTION-DESORPTION PHASE NOISE

During the past two decades a considerable effort has been made to develop radio-frequency (RF) resonators which are fabricated using the micro/nanoelectro-mechanical systems (MEMS/NEMS) technologies, in order to replace conventional large off-chip components in wireless transceivers and other high-speed electronic systems.The first part of the paper presents an overview of RF MEMS and NEMS resonators, including those based on two-dimensional crystals (e.g. graphene). The frequency tuning in MEMS/NEMS resonators is then analyzed. Improvements that would be necessary in order for MEMS/NEMS resonators to meet the requirements of wireless systems are also discussed.The analysis of noise of RF MEMS/NEMS resonators and oscillators is especially important in modern wireless communication systems due to increasingly stringent requirements regarding the acceptable noise level in every next generation. The second part of the paper presents the analysis of adsorption-desorption (AD) noise in RF MEMS/NEMS resonators, which becomes pronounced with the decrease of components' dimensions, and is not sufficiently elaborated in the existing literature about such components. Finally, a theoretical model of phase noise in RF MEMS/NEMS oscillators will be presented, with a special emphasize on the influence of the resonator AD noise on the oscillator phase noise

Saw-Less radio receivers in CMOS

Smartphones play an essential role in our daily life. Connected to the internet, we can easily keep in touch with family and friends, even if far away, while ever more apps serve us in numerous ways. To support all of this, higher data rates are needed for ever more wireless users, leading to a very crowded radio frequency spectrum. To achieve high spectrum efficiency while reducing unwanted interference, high-quality band-pass filters are needed. Piezo-electrical Surface Acoustic Wave (SAW) filters are conventionally used for this purpose, but such filters need a dedicated design for each new band, are relatively bulky and also costly compared to integrated circuit chips. Instead, we would like to integrate the filters as part of the entire wireless transceiver with digital smartphone hardware on CMOS chips. The research described in this thesis targets this goal. It has recently been shown that N-path filters based on passive switched-RC circuits can realize high-quality band-select filters on CMOS chips, where the center frequency of the filter is widely tunable by the switching-frequency. As CMOS downscaling following Moore’s law brings us lower clock-switching power, lower switch on-resistance and more compact metal-to-metal capacitors, N-path filters look promising. This thesis targets SAW-less wireless receiver design, exploiting N-path filters. As SAW-filters are extremely linear and selective, it is very challenging to approximate this performance with CMOS N-path filters. The research in this thesis proposes and explores several techniques for extending the linearity and enhancing the selectivity of N-path switched-RC filters and mixers, and explores their application in CMOS receiver chip designs. First the state-of-the-art in N-path filters and mixer-first receivers is reviewed. The requirements on the main receiver path are examined in case SAW-filters are removed or replaced by wideband circulators. The feasibility of a SAW-less Frequency Division Duplex (FDD) radio receiver is explored, targeting extreme linearity and compression Irequirements. A bottom-plate mixing technique with switch sharing is proposed. It improves linearity by keeping both the gate-source and gate-drain voltage swing of the MOSFET-switches rather constant, while halving the switch resistance to reduce voltage swings. A new N-path switch-RC filter stage with floating capacitors and bottom-plate mixer-switches is proposed to achieve very high linearity and a second-order voltage-domain RF-bandpass filter around the LO frequency. Extra out-of-band (OOB) rejection is implemented combined with V-I conversion and zero-IF frequency down-conversion in a second cross-coupled switch-RC N-path stage. It offers a low-ohmic high-linearity current path for out-of-band interferers. A prototype chip fabricated in a 28 nm CMOS technology achieves an in-band IIP3 of +10 dBm , IIP2 of +42 dBm, out-of-band IIP3 of +44 dBm, IIP2 of +90 dBm and blocker 1-dB gain-compression point of +13 dBm for a blocker frequency offset of 80 MHz. At this offset frequency, the measured desensitization is only 0.6 dB for a 0-dBm blocker, and 3.5 dB for a 10-dBm blocker at 0.7 GHz operating frequency (i.e. 6 and 9 dB blocker noise figure). The chip consumes 38-96 mW for operating frequencies of 0.1-2 GHz and occupies an active area of 0.49 mm2. Next, targeting to cover all frequency bands up to 6 GHz and achieving a noise figure lower than 3 dB, a mixer-first receiver with enhanced selectivity and high dynamic range is proposed. Capacitive negative feedback across the baseband amplifier serves as a blocker bypassing path, while an extra capacitive positive feedback path offers further blocker rejection. This combination of feedback paths synthesizes a complex pole pair at the input of the baseband amplifier, which is up-converted to the RF port to obtain steeper RF-bandpass filter roll-off than the conventional up-converted real pole and reduced distortion. This thesis explains the circuit principle and analyzes receiver performance. A prototype chip fabricated in 45 nm Partially Depleted Silicon on Insulator (PDSOI) technology achieves high linearity (in-band IIP3 of +3 dBm, IIP2 of +56 dBm, out-of-band IIP3 = +39 dBm, IIP2 = +88 dB) combined with sub-3 dB noise figure. Desensitization due to a 0-dBm blocker is only 2.2 dB at 1.4 GHz operating frequency. IIFinally, to demonstrate the performance of the implemented blocker-tolerant receiver chip designs, a test setup with a real mobile phone is built to verify the sensitivity of the receiver chip for different practical blocking scenarios

Design of Analog-to-Digital Converters with Embedded Mixing for Ultra-Low-Power Radio Receivers

In the field of radio receivers, down-conversion methods usually rely on one (or more) explicit mixing stage(s) before the analog-to-digital converter (ADC). These stages not only contribute to the overall power consumption but also have an impact on area and can compromise the receiver’s performance in terms of noise and linearity. On the other hand, most ADCs require some sort of reference signal in order to properly digitize an analog input signal. The implementation of this reference signal usually relies on bandgap circuits and reference buffers to generate a constant, stable, dc signal. Disregarding this conventional approach, the work developed in this thesis aims to explore the viability behind the usage of a variable reference signal. Moreover, it demonstrates that not only can an input signal be properly digitized, but also shifted up and down in frequency, effectively embedding the mixing operation in an ADC. As a result, ADCs in receiver chains can perform double-duty as both a quantizer and a mixing stage. The lesser known charge-sharing (CS) topology, within the successive approximation register (SAR) ADCs, is used for a practical implementation, due to its feature of “pre-charging” the reference signal prior to the conversion. Simulation results from an 8-bit CS-SAR ADC designed in a 0.13 μm CMOS technology validate the proposed technique

Advanced CMOS Integrated Circuit Design and Application

The recent development of various application systems and platforms, such as 5G, B5G, 6G, and IoT, is based on the advancement of CMOS integrated circuit (IC) technology that enables them to implement high-performance chipsets. In addition to development in the traditional fields of analog and digital integrated circuits, the development of CMOS IC design and application in high-power and high-frequency operations, which was previously thought to be possible only with compound semiconductor technology, is a core technology that drives rapid industrial development. This book aims to highlight advances in all aspects of CMOS integrated circuit design and applications without discriminating between different operating frequencies, output powers, and the analog/digital domains. Specific topics in the book include: Next-generation CMOS circuit design and application; CMOS RF/microwave/millimeter-wave/terahertz-wave integrated circuits and systems; CMOS integrated circuits specially used for wireless or wired systems and applications such as converters, sensors, interfaces, frequency synthesizers/generators/rectifiers, and so on; Algorithm and signal-processing methods to improve the performance of CMOS circuits and systems

Flexible Receivers in CMOS for Wireless Communication

Consumers are pushing for higher data rates to support more services that are introduced in mobile applications. As an example, a few years ago video-on-demand was only accessed through landlines, but today wireless devices are frequently used to stream video. To support this, more flexible network solutions have merged in 4G, introducing new technical problems to the mobile terminal. New techniques are thus needed, and this dissertation explores five different ideas for receiver front-ends, that are cost-efficient and flexible both in performance and operating frequency. All ideas have been implemented in chips fabricated in 65 nm CMOS technology and verified by measurements. Paper I explores a voltage-mode receiver front-end where sub-threshold positive feedback transistors are introduced to increase the linearity in combination with a bootstrapped passive mixer. Paper II builds on the idea of 8-phase harmonic rejection, but simplifies it to a 6-phase solution that can reject noise and interferers at the 3rd order harmonic of the local oscillator frequency. This provides a good trade-off between the traditional quadrature mixer and the 8- phase harmonic rejection mixer. Furthermore, a very compact inductor-less low noise amplifier is introduced. Paper III investigates the use of global negative feedback in a receiver front-end, and also introduces an auxiliary path that can cancel noise from the main path. In paper IV, another global feedback based receiver front-end is designed, but with positive feedback instead of negative. By introducing global positive feedback, the resistance of the transistors in a passive mixer-first receiver front-end can be reduced to achieve a lower noise figure, while still maintaining input matching. Finally, paper V introduces a full receiver chain with a single-ended to differential LNA, current-mode downconversion mixers, and a baseband circuity that merges the functionalities of the transimpedance amplifier, channel-select filter, and analog-to-digital converter into one single power-efficient block

High performance RF and baseband building blocks for wireless receivers

Because of the unique architecture of wireless receivers, a designer must understand both the high frequency aspects as well as the low-frequency analog considerations for different building blocks of the receiver. The primary goal of this research work is to explore techniques for implementing high performance RF and baseband building blocks for wireless applications. Several novel techniques to improve the performance of analog building blocks are presented. An enhanced technique to couple two LC resonators is presented which does not degrade the loaded quality factor of the resonators which results in an increased dynamic range. A novel technique to automatically tune the quality factor of LC resonators is presented. The proposed scheme is stable and fast and allows programming both the quality factor and amplitude response of the LC filter. To keep the oscillation amplitude of LC VCOs constant and thus achieving a minimum phase noise and a reliable startup, a stable amplitude control loop is presented. The proposed scheme has been also used in a master-slave quality factor tuning of LC filters. An efficient and low-cost architecture for a 3.1GHz-10.6GHz ultra-wide band frequency synthesizer is presented. The proposed scheme is capable of generating 14A novel pseudo-differential transconductance amplifier is presented. The proposed scheme takes advantage of the second-order harmonic available at the output current of pseudo-differential structure to cancel the third-order harmonic distortion. A novel nonlinear function is proposed which inherently removes the third and the fifth order harmonics at its output signal. The proposed nonlinear block is used in a bandpass-based oscillator to generate a highly linear sinusoidal output. Finally, a linearized BiCMOS transconductance amplifier is presented. This transconductance is used to build a third-order linear phase low pass filter with a cut-off frequency of 264MHz for an ultra-wide band receiver. carrier frequencies