13 research outputs found

    Software Reliability Growth Model Based on Linear Failure Rate Distribution

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    A Non Homogenous Poisson Process (NHPP) with its mean value function generated by the cumulative distribution function of linear failure rate distribution is considered. It is modeled to assess the failure phenomenon of a developed software. When the failure data is in the form of number of failures in a given interval of time the model parameters are estimated by moment type estimation method and the performance of the model using three data sets is discussed in comparison with similar other models

    Cost Estimation Approach for Scrum Agile Software Process Model

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    The software development in the industry is moving towards agile due to the advantages provided by the agile development process. Main advantages of agile software development process are: delivering high quality software in shorter intervals and embracing change. Testing is a vital activity in software development process model, for delivering a high quality software product. Often testing accounts for more project effort and time than any other software development activities. The software testing cost estimation is one of the most important managerial activities related to resource allocation, project planning and to control overall cost of the software development. Several models have been proposed by various authors to address the issue of effort and cost estimation. Most of the models are directly or indirectly depend on the source code of the software product. But, majority of the testing in software organizations is done in black-box environment, where the source code of the software is not available to the testing teams. In this paper, an alternative approach to software testing cost estimation for scrum agile software process model, by considering various testing activities involved in black-box testing environment is presented. The proposed approach is applied on four real world case studies and found that this approach provides more accurate estimation of the testing effort and cost, and helps the software managers in controlling the overrun of the project schedules and project costs

    Entorno de test automatizado para la verificación de microcontroladores basado en el software de National Instruments.

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    Castellano: Verificar la funcionalidad de las tarjetas de desarrollo a utilizar en cualquier proyecto, es fundamental para asegurar que los errores generados durante el desarrollo se deben a la programación y no a la disfunción del hardware. Con el auge de nuevas tecnologías como la RISC-V, que además son de código abierto, la verificación se convierte en más importante dado que las opciones en el mercado son muy amplias y los estándares de verificación de hardware varían mucho entre fabricantes. Se ha implementado un entorno de test utilizando LabVIEW y TestStand para verificar los periféricos de varias tarjetas de evaluación necesarios para realizar el control de velocidad de un motor síncrono de imanes permanentes (PMSM), utilizando la técnica FOC, de control de campo orientado. Para dicho algoritmo es necesario el uso de los GPIOs de la tarjeta, generación PWM, lectura ADC, decoder y comunicaciones SPI e I2C. Se ha implementado un protocolo de comunicación serial de tamaño variable específico para el testeo de dispositivos para comunicar el PC y el dispositivo a testear utilizando UART. Las pruebas necesarias para realizar los tests han sido programadas en dos tarjetas de desarrollo diferentes, una con arquitectura RISC-V del fabricante GigaDevice y una Delfino de Texas Instruments. Se ha probado el software LabVIEW NXG para la implementación de las pruebas, pero se han obtenido resultados muy negativos, dado los errores que tiene y que National Instruments no va a sacar más versiones. Ambas tarjetas de desarrollo han superado el entorno de verificación exitosamente, concluyendo que son aptas para el control del motor. Además, se ha programado el control en la tarjeta que contiene la RISC-V, y se ha comprobado que puede controlar el motor.Euskera: Garapen txartelen funtzionalitatea berifikatzea ezinbestekoa da, proiektu batean gertatu daitezkeen akatsak programazioagatik sortuak direla eta hardwarraren disfunzioaren erru ez direla zihurtatzeko. RISC-Va bezalako kode irekiko teknologia berrien gorakadarekin gainera, berifikazioa are garrantzitsuagoa bihurtzen da, merkatuko aukerak asko zabaltzen direlako eta ekoizle desberdinek egindako probak oso desberdinak izan daitezkeelako. LabVIEW eta TestStand softwareak erabiliz, test ingurune bat implementatu da iman permanenteko motor sinkrono baten kontrolerako beharrezkoak diren funtzionalitateak berifikatzeko, FOC teknika erabiliz. Kontrol horren algoritmoa implementazeko GPIOen erabilera, ADCarena, PWMarena, decoder batena, eta SPI eta I2C interfazeak beharrezkoak diren. Ingurunea exekutatu ahal izateko tamaina aldakorreko komunikazio protokolo bat garatu da, PCa eta testeatuko diren gailuak UART bidez komunikatzeko. Testak exekutatzeko beharrezkoak diren probak inplementatzeko bi garapen txartel desberdin erabili dira, bat GigaDevice ekoizlearena eta RISC-V arkitekturaduna, bestea, aldiz, Texas Instruments-en Delfino bat. Probak inplementatzeko orduan LabVIEW NXG softwarea probatu da, baina lortutako emaitzak ez dira onak izan, akats asko baititu eta gainera National Instruments-ek bertsio berri gehiago aterako ez baititu. Erabilitako bi garapen txartelek arazo gabe gainditu dute berifikazioa. Gainera, RISC-V a duen txartelean motorraren kontrola implementatu da, eta motorra arazorik gabe kontrolatzen duela ikusi da.English: Functional verification of the development cards that are going to be used in a project, is fundamental to ensure that the errors that could occur during the development of the project are caused by the programming and not by a hardware malfunction. With the boom of new technologies as the RISC-V in the last years, that much are also open source, lots of manufacturers have been developing their own products based on that technology. Quality control may vary a lot between manufacturers, so hardware verification gains even more importance. A test environment has been implemented using LabVIEW and TestStand for the verification of the interfaces needed for a control of a permanent magnet synchronous motor using the Field Oriented Control (FOC) technique. Those interfaces are the GPIOs of the card, the ADC, PWM generators, a decoder and SPI and I2C communications. A unit testing specific variable length communication protocol has been used for the communication between the PC and the device under test (DUT). The tests needed to execute the environment have been implemented in two different development cards, of the them is a GigaDevice card that uses RISC-V architecture, and the other one is a Texas Instruments Delfino. National Instruments new hardware LabVIEW NXG has been tested for developing the environment, but the results obtained have been unfavourable, given the amount of bugs that the software has and the fact that Nationaln Instruments is not going to release more versions of the software. Both of the development cards have sucesfully surpassed the verification environment without any issues. In addittion, the FOC control has been implemented on the RISC-V, and it has been verifyed that the board can control the motor correctly

    Geometric Approaches to Statistical Defect Prediction and Learning

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    Software quality is directly correlated with the number of defects in software systems. As the complexity of software increases, manual inspection of software becomes prohibitively expensive. Thus, defect prediction is of paramount importance to project managers in allocating the limited resources effectively as well as providing many advantages such as the accurate estimation of project costs and schedules. This thesis addresses the issues of defect prediction and learning in the geometric framework using statistical quality control and genetic algorithms. A software defect prediction model using the geometric concept of operating characteristic curves is proposed. The main idea behind this predictor is to use geometric insight in helping construct an efficient prediction method to reliably predict the cumulative number of defects during the software development process. The performance of the proposed approach is validated on real data from actual software projects, and the experimental results demonstrate a much improved performance of the proposed statistical method in predicting defects. In the same vein, two defect learning predictors based on evolutionary algorithms are also proposed. These predictors use genetic programming as feature constructor method. The first predictor constructs new features based primarily on the geometrical characteristics of the original data. Then, an independent classifier is applied and the performance of feature selection method is measured. The second predictor uses a built-in classifier which automatically gets tuned for the constructed features. Experimental results on a NASA static metric dataset demonstrate the feasibility of the proposed genetic programming based approaches

    Resource allocation and optimal release time in software systems

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    Software quality is directly correlated with the number of defects in software systems. As the complexity of software increases, manual inspection of software becomes prohibitively expensive. Thus, defect prediction is of paramount importance to project managers in allocating the limited resources effectively as well as providing many advantages such as the accurate estimation of project costs and schedules. This thesis addresses the issues of statistical fault prediction modeling, software resource allocation, and optimal software release and maintenance policy. A software defect prediction model using operating characteristic curves is presented. The main idea behind this predictor is to use geometric insight in helping construct an efficient prediction method to reliably predict the cumulative number of defects during the software development process. Motivated by the widely used concept of queue models in communication systems and information processing systems, a resource allocation model which answers managerial questions related to project status and scheduling is then introduced. Using the proposed allocation model, managers will be more certain about making resource allocation decisions as well as measuring the system reliability and the quality of service provided to customers in terms of the expected response time. Finally, a novel stochastic model is proposed to describe the cost behavior of the operation, and estimate the optimal time by minimizing a cost function via artificial neural networks. Further, a detailed analysis of software release time and maintenance decision is also presented. The performance of the proposed approaches is validated on real data from actual SAP projects, and the experimental results demonstrate a compelling motivation for improved software qualit

    Software reliability modeling and analysis

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    Ph.DDOCTOR OF PHILOSOPH

    Fault detection and correction modeling of software systems

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    Ph.DDOCTOR OF PHILOSOPH
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