Drawing graphs for cartographic applications

Graph Drawing is a relatively young area that combines elements of graph theory, algorithms, (computational) geometry and (computational) topology. Research in this field concentrates on developing algorithms for drawing graphs while satisfying certain aesthetic criteria. These criteria are often expressed in properties like edge complexity, number of edge crossings, angular resolutions, shapes of faces or graph symmetries and in general aim at creating a drawing of a graph that conveys the information to the reader in the best possible way. Graph drawing has applications in a wide variety of areas which include cartography, VLSI design and information visualization. In this thesis we consider several graph drawing problems. The first problem we address is rectilinear cartogram construction. A cartogram, also known as value-by-area map, is a technique used by cartographers to visualize statistical data over a set of geographical regions like countries, states or counties. The regions of a cartogram are deformed such that the area of a region corresponds to a particular geographic variable. The shapes of the regions depend on the type of cartogram. We consider rectilinear cartograms of constant complexity, that is cartograms where each region is a rectilinear polygon with a constant number of vertices. Whether a cartogram is good is determined by how closely the cartogram resembles the original map and how precisely the area of its regions describe the associated values. The cartographic error is defined for each region as jAc¡Asj=As, where Ac is the area of the region in the cartogram and As is the specified area of that region, given by the geographic variable to be shown. In this thesis we consider the construction of rectilinear cartograms that have correct adjacencies of the regions and zero cartographic error. We show that any plane triangulated graph admits a rectilinear cartogram where every region has at most 40 vertices which can be constructed in O(nlogn) time. We also present experimental results that show that in practice the algorithm works significantly better than suggested by the complexity bounds. In our experiments on real-world data we were always able to construct a cartogram where the average number of vertices per region does not exceed five. Since a rectangle has four vertices, this means that most of the regions of our rectilinear car tograms are in fact rectangles. Moreover, the maximum number vertices of each region in these cartograms never exceeded ten. The second problem we address in this thesis concerns cased drawings of graphs. The vertices of a drawing are commonly marked with a disk, but differentiating between vertices and edge crossings in a dense graph can still be difficult. Edge casing is a wellknown method—used, for example, in electrical drawings, when depicting knots, and, more generally, in information visualization—to alleviate this problem and to improve the readability of a drawing. A cased drawing orders the edges of each crossing and interrupts the lower edge in an appropriate neighborhood of the crossing. One can also envision that every edge is encased in a strip of the background color and that the casing of the upper edge covers the lower edge at the crossing. If there are no application-specific restrictions that dictate the order of the edges at each crossing, then we can in principle choose freely how to arrange them. However, certain orders will lead to a more readable drawing than others. In this thesis we formulate aesthetic criteria for a cased drawing as optimization problems and solve these problems. For most of the problems we present either a polynomial time algorithm or demonstrate that the problem is NP-hard. Finally we consider a combinatorial question in computational topology concerning three types of objects: closed curves in the plane, surfaces immersed in the plane, and surfaces embedded in space. In particular, we study casings of closed curves in the plane to decide whether these curves can be embedded as the boundaries of certain special surfaces. We show that it is NP-complete to determine whether an immersed disk is the projection of a surface embedded in space, or whether a curve is the boundary of an immersed surface in the plane that is not constrained to be a disk. However, when a casing is supplied with a self-intersecting curve, describing which component of the curve lies above and which below at each crossing, we can determine in time linear in the number of crossings whether the cased curve forms the projected boundary of a surface in space. As a related result, we show that an immersed surface with a single boundary curve that crosses itself n times has at most 2n=2 combinatorially distinct spatial embeddings and we discuss the existence of fixed-parameter tractable algorithms for related problems

Discrete Geometry

[no abstract available

Transistor-Level Layout of Integrated Circuits

In this dissertation, we present the toolchain BonnCell and its underlying algorithms. It has been developed in close cooperation with the IBM Corporation and automatically generates the geometry for functional groups of 2 to approximately 50 transistors. Its input consists of a set of transistors, including properties like their sizes and their types, a specification of their connectivity, and parameters to flexibly control the technological framework as well as the algorithms' behavior. Using this data, the tool computes a detailed geometric realization of the circuit as polygonal shapes on 16 layers. To this end, a placement routine configures the transistors and arranges them in the plane, which is the main subject of this thesis. Subsequently, a routing engine determines wires connecting the transistors to ensure the circuit's desired functionality. We propose and analyze a family of algorithms that arranges sets of transistors in the plane such that a multi-criteria target function is optimized. The primary goal is to obtain solutions that are as compact as possible because chip area is a valuable resource in modern techologies. In addition to the core algorithms we formulate variants that handle particularly structured instances in a suitable way. We will show that for 90% of the instances in a representative test bed provided by IBM, BonnCell succeeds to generate fully functional layouts including the placement of the transistors and a routing of their interconnections. Moreover, BonnCell is in wide use within IBM's groups that are concerned with transistor-level layout - a task that has been performed manually before our automation was available. Beyond the processing of isolated test cases, two large-scale examples for applications of the tool in the industry will be presented: On the one hand the initial design phase of a large SRAM unit required only half of the expected 3 month period, on the other hand BonnCell could provide valuable input aiding central decisions in the early concept phase of the new 14 nm technology generation

VLSI Routing for Advanced Technology

Routing is a major step in VLSI design, the design process of complex integrated circuits (commonly known as chips). The basic task in routing is to connect predetermined locations on a chip (pins) with wires which serve as electrical connections. One main challenge in routing for advanced chip technology is the increasing complexity of design rules which reflect manufacturing requirements. In this thesis we investigate various aspects of this challenge. First, we consider polygon decomposition problems in the context of VLSI design rules. We introduce different width notions for polygons which are important for width-dependent design rules in VLSI routing, and we present efficient algorithms for computing width-preserving decompositions of rectilinear polygons into rectangles. Such decompositions are used in routing to allow for fast design rule checking. A main contribution of this thesis is an O(n) time algorithm for computing a decomposition of a simple rectilinear polygon with n vertices into O(n) rectangles, preseverving two-dimensional width. Here the two-dimensional width at a point of the polygon is defined as the edge length of a largest square that contains the point and is contained in the polygon. In order to obtain these results we establish a connection between such decompositions and Voronoi diagrams. Furthermore, we consider implications of multiple patterning and other advanced design rules for VLSI routing. The main contribution in this context is the detailed description of a routing approach which is able to manage such advanced design rules. As a main algorithmic concept we use multi-label shortest paths where certain path properties (which model design rules) can be enforced by defining labels assigned to path vertices and allowing only certain label transitions. The described approach has been implemented in BonnRoute, a VLSI routing tool developed at the Research Institute for Discrete Mathematics, University of Bonn, in cooperation with IBM. We present experimental results confirming that a flow combining BonnRoute and an external cleanup step produces far superior results compared to an industry standard router. In particular, our proposed flow runs more than twice as fast, reduces the via count by more than 20%, the wiring length by more than 10%, and the number of remaining design rule errors by more than 60%. These results obtained by applying our multiple patterning approach to real-world chip instances provided by IBM are another main contribution of this thesis. We note that IBM uses our proposed combined BonnRoute flow as the default tool for signal routing

Schematics of Graphs and Hypergraphs

Graphenzeichnen als ein Teilgebiet der Informatik befasst sich mit dem Ziel Graphen oder deren Verallgemeinerung Hypergraphen geometrisch zu realisieren. Beschränkt man sich dabei auf visuelles Hervorheben von wesentlichen Informationen in Zeichenmodellen, spricht man von Schemata. Hauptinstrumente sind Konstruktionsalgorithmen und Charakterisierungen von Graphenklassen, die für die Konstruktion geeignet sind. In dieser Arbeit werden Schemata für Graphen und Hypergraphen formalisiert und mit den genannten Instrumenten untersucht. In der Dissertation wird zunächst das „partial edge drawing“ (kurz: PED) Modell für Graphen (bezüglich gradliniger Zeichnung) untersucht. Dabei wird um Kreuzungen im Zentrum der Kante visuell zu eliminieren jede Kante durch ein kreuzungsfreies Teilstück (= Stummel) am Start- und am Zielknoten ersetzt. Als Standard hat sich eine PED-Variante etabliert, in der das Längenverhältnis zwischen Stummel und Kante genau 1⁄4 ist (kurz: 1⁄4-SHPED). Für 1⁄4-SHPEDs werden Konstruktionsalgorithmen, Klassifizierung, Implementierung und Evaluation präsentiert. Außerdem werden PED-Varianten mit festen Knotenpositionen und auf Basis orthogonaler Zeichnungen erforscht. Danach wird das BUS Modell für Hypergraphen untersucht, in welchem Hyperkanten durch fette horizontale oder vertikale – als BUS bezeichnete – Segmente repräsentiert werden. Dazu wird eine vollständige Charakterisierung von planaren Inzidenzgraphen von Hypergraphen angegeben, die eine planare Zeichnung im BUS Modell besitzen, und diverse planare BUS-Varianten mit festen Knotenpositionen werden diskutiert. Zum Schluss wird erstmals eine Punktmenge von subquadratischer Größe angegeben, die eine planare Einbettung (Knoten werden auf Punkte abgebildet) von 2-außenplanaren Graphen ermöglicht

Proceedings of the 8th Cologne-Twente Workshop on Graphs and Combinatorial Optimization

International audienceThe Cologne-Twente Workshop (CTW) on Graphs and Combinatorial Optimization started off as a series of workshops organized bi-annually by either Köln University or Twente University. As its importance grew over time, it re-centered its geographical focus by including northern Italy (CTW04 in Menaggio, on the lake Como and CTW08 in Gargnano, on the Garda lake). This year, CTW (in its eighth edition) will be staged in France for the first time: more precisely in the heart of Paris, at the Conservatoire National d’Arts et Métiers (CNAM), between 2nd and 4th June 2009, by a mixed organizing committee with members from LIX, Ecole Polytechnique and CEDRIC, CNAM