Case studies on lithography-friendly vlsi circuit layout

Moore’s Law has driven a continuous demand for decreasing feature sizes used in Very Large Scale Integrated (VLSI) technology which has outpaced the solutions offered by lithography hardware. Currently, a light wavelength of 193nm is being used to print sub-65nm features. This introduces process variations which cause mismatches between desired and actual wafer feature sizes. However, the layout which affects the printability of a circuit can be modified in a manner which can make it more lithography-friendly. In this work, we intend to implement these modifications as a series of perturbations on the initial layout generated by the CAD tool for the circuit. To implement these changes we first calculate the feature variations offline on the boundaries of all possible standard cell pairs used in the circuit layout and record them in a Look-Up Table (LUT). After the CAD tool generates the initial placement of the circuit, we use the LUT to estimate the variations on the boundaries of all the standard cells. Depending on the features which may have the highest feature variations we assign a cost to the layout and our aim is now to reduce the cost of the layout after implementing perturbations which could be a simple cell flip or swap with a neighboring cell. The algorithm used to generate a circuit placement with a low cost is Simulated Annealing which allows a high probability for a solution with a higher cost to be selected during the initial iterations and as time goes on it tends closer to the greedy algorithm. The idea here is to avoid a locally optimum solution. It is also essential to minimize the impact of the iterations performed on the initial solution in terms of wirelength, vias and routing congestion. We validate our procedure on ISCAS85 benchmark circuits by simulating dose and defocus variations using the Mentor tool Calibre LFD. We obtain a reduction of greater 20% in the number of instances with the highest cell boundary feature variations. The wirelength and the number of vias showed an increase of roughly 2.2-8.8% and 1.2- 7.8% respectively for different circuits. The routing congestion by and large remains unaffected

Case studies on lithography-friendly vlsi circuit layout

Moore’s Law has driven a continuous demand for decreasing feature sizes used in Very Large Scale Integrated (VLSI) technology which has outpaced the solutions offered by lithography hardware. Currently, a light wavelength of 193nm is being used to print sub-65nm features. This introduces process variations which cause mismatches between desired and actual wafer feature sizes. However, the layout which affects the printability of a circuit can be modified in a manner which can make it more lithography-friendly. In this work, we intend to implement these modifications as a series of perturbations on the initial layout generated by the CAD tool for the circuit. To implement these changes we first calculate the feature variations offline on the boundaries of all possible standard cell pairs used in the circuit layout and record them in a Look-Up Table (LUT). After the CAD tool generates the initial placement of the circuit, we use the LUT to estimate the variations on the boundaries of all the standard cells. Depending on the features which may have the highest feature variations we assign a cost to the layout and our aim is now to reduce the cost of the layout after implementing perturbations which could be a simple cell flip or swap with a neighboring cell. The algorithm used to generate a circuit placement with a low cost is Simulated Annealing which allows a high probability for a solution with a higher cost to be selected during the initial iterations and as time goes on it tends closer to the greedy algorithm. The idea here is to avoid a locally optimum solution. It is also essential to minimize the impact of the iterations performed on the initial solution in terms of wirelength, vias and routing congestion. We validate our procedure on ISCAS85 benchmark circuits by simulating dose and defocus variations using the Mentor tool Calibre LFD. We obtain a reduction of greater 20% in the number of instances with the highest cell boundary feature variations. The wirelength and the number of vias showed an increase of roughly 2.2-8.8% and 1.2- 7.8% respectively for different circuits. The routing congestion by and large remains unaffected

Design for manufacturing (DFM) in submicron VLSI design

As VLSI technology scales to 65nm and below, traditional communication between design and manufacturing becomes more and more inadequate. Gone are the days when designers simply pass the design GDSII file to the foundry and expect very good man¬ufacturing and parametric yield. This is largely due to the enormous challenges in the manufacturing stage as the feature size continues to shrink. Thus, the idea of DFM (Design for Manufacturing) is getting very popular. Even though there is no universally accepted definition of DFM, in my opinion, one of the major parts of DFM is to bring manufacturing information into the design stage in a way that is understood by designers. Consequently, designers can act on the information to improve both manufacturing and parametric yield. In this dissertation, I will present several attempts to reduce the gap between design and manufacturing communities: Alt-PSM aware standard cell designs, printability improve¬ment for detailed routing and the ASIC design flow with litho aware static timing analysis. Experiment results show that we can greatly improve the manufacturability of the designs and we can reduce design pessimism significantly for easier design closure

Analog layout design automation: ILP-based analog routers

The shrinking design window and high parasitic sensitivity in the advanced technology have imposed special challenges on the analog and radio frequency (RF) integrated circuit design. In this thesis, we propose a new methodology to address such a deficiency based on integer linear programming (ILP) but without compromising the capability of handling any special constraints for the analog routing problems. Distinct from the conventional methods, our algorithm utilizes adaptive resolutions for various routing regions. For a more congested region, a routing grid with higher resolution is employed, whereas a lower-resolution grid is adopted to a less crowded routing region. Moreover, we strengthen its speciality in handling interconnect width control so as to route the electrical nets based on analog constraints while considering proper interconnect width to address the acute interconnect parasitics, mismatch minimization, and electromigration effects simultaneously. In addition, to tackle the performance degradation due to layout dependent effects (LDEs) and take advantage of optical proximity correction (OPC) for resolution enhancement of subwavelength lithography, in this thesis we have also proposed an innovative LDE-aware analog layout migration scheme, which is equipped with our special routing methodology. The LDE constraints are first identified with aid of a special sensitivity analysis and then satisfied during the layout migration process. Afterwards the electrical nets are routed by an extended OPC-inclusive ILP-based analog router to improve the final layout image fidelity while the routability and analog constraints are respected in the meantime. The experimental results demonstrate the effectiveness and efficiency of our proposed methods in terms of both circuit performance and image quality compared to the previous works

Limitations of Proximity Lithography Printing:Simulations, Experiments, and Applications

Photolithography is one of the earliest technologies used to transfer patterns to a substrate. It is also known as optical lithography since it uses light to transfer the pattern. The main exposure techniques exist in the industry are projection printing, contact printing, and proximity printing. Projection printing technology uses optical elements between mask and wafer to project the feature on the mask to the wafer. This is very expensive and delivers the highest resolution. In contact printing, the mask and wafer are in contact with each other and in proximity printing, the mask is kept at some proximity distance away from the wafer. Proximity printing is an easy and cost effective printing technique because the damage to the mask will be less and also no optical elements between mask and wafer are used. The main drawback of the proximity printing is the diffraction effect caused by the proximity gap between mask and wafer, which limits the resolution. The main objective of this thesis is to study the limitations of proximity printing and to increase its resolution. To study the limitations, different types of design strategies and verification methods are used in the thesis. First is the simulation technique which is performed with GenISys Layout LAB. This is specially designed for proximity printing. The software gives the aerial image and final resist pattern as output. The most interesting and important aspect is the second verification technique which is the experimental setup. A measurement setup has been built to study the light propagation from different masks and to study the aerial image at different proximity gaps. The setup is known as High Resolution Interference Microscopy (HRIM). The setup is basically a Mach- Zehnder interferometer having different light sources, sample plane and reference arm which are used according to the samples. The final verification is achieved using the mask aligner. Both the simulation and experiments are carried out using a special illumination optics called MO exposure optics from Süss MicroOptics. The thesis mainly focuses on the rule based optical proximity correction a technique which is a simple method for mass production. Correction structures are designed for one dimensional and two dimensional features in amplitude masks. Adding lines near the edge to improve the edge slope will be discussed as the one dimensional correction. The different intensity cutting planes and the comparison between simulation and experimental results will be discussed along with that. A unified correction structure is designed to solve corner rounding problem and will be studied as the two dimensional study. The structure is defined to print different line widths at single proximity gap on single exposure. Usually, all the structures in the amplitude mask are studied with their aerial image intensities at different proximity gaps. But, here the study extends to phase evaluation also. The measurement technique can measure both intensity and phase evolution from the mask structures. Phase evolution from amplitude correction features will be discussed and how the phase modulates the intensity patterns is also studied. The role of fundamental principles like phase singularities, phase shifts are also discussed to find its effects on proximity printing structures. The study also leads to the intensity and phase propagation from phase shifting mask (PSM) . The structure evaluated is a group of corners in PSM

Baukastenbasierte Entwicklungsmethodik für die rechnerunterstützte Konstruktion von Mikrosystemen

In der vorliegenden Arbeit wird eine Methodik vorgestellt, die den Entwickler von Mikrosystemen von der Entwicklung einzelner Komponenten bis zum Entwurf komplexer Mikrosysteme, die aus einer Vielzahl von Materialien bestehen können, unterstützt. Dazu wird zunächst ausgehend von bekannten Vorgehensmodellen der Produktentwicklung ein Vorschlag für ein an die Besonderheiten des Mikrosystementwurfs angepasstes Vorgehensmodell entwickelt welches den verhaltensnahen und den fertigungsnahen Entwurf vereint. Dabei wird insbesondere darauf geachtet, dass es ungeachtet der Ausrichtung der Entwurfsstrategie einen gemeinsamen Einstiegspunkt in das Vorgehensmodell gibt. Der Systementwurf in dem von den Anforderungen eine Funktions-, bzw. Wirkstruktur abgeleitet wird, ist sowohl für den verhaltensnahen als auch für den fertigungsnahen Entwurf relevant. Ausgehend von der Wirkstruktur sieht das Vorgehensmodell dann prinzipiell zwei Wege vor, die zunächst zur Ableitung eines dreidimensionalen Modells, später zum gefertigten Mikrosystem führen. Die Analyse des Stands der Forschung hat gezeigt, dass die bisher entwickelten Entwurfswerkzeuge hauptsächlich den verhaltensnahen Entwurf unterstützen. Die bekannten Ansätze zur fertigungsnahen Entwurfsunterstützung vernachlässigen weitestgehend den Entwurf des Maskenlayouts. Im Bereich der Baukästen wurden hauptsächlich Systembaukästen aufgebaut, die einzelne Mikrosysteme über definierte Schnittstellen miteinander verbinden. Daher wurde ein System entwickelt, welches eine Lücke im Bereich des Komponentenentwurfs schließt. Mit Hilfe von Bausteinen auf Komponentenebene kann eine Möglichkeit aufgezeigt werden wie ein kombinierter Layout- und Prozessentwurf die technologieübergreifende Nutzung von bereits erfolgreich gefertigten Lösungselementen ermöglicht. Das System wurde in einen Softwareprototyp umgesetzt und mit einer zentralen Datenbank verbunden. Einen Aspekt des Komponentenentwurfs spiegelt die detaillierte Simulation konkreter Prozessschritte wider. Gerade im Umgang mit Prozessen der UV-Tiefenlithographie hat sich im Verlauf der Arbeit gezeigt, dass Beugungserscheinungen die strukturgetreue Abbildung der Maskengeometrie verhindern. Es ist daher sinnvoll, die Belichtungsintensität auf der Resistoberfläche vorhersagen zu können, um das Maskenlayout ggf. anzupassen. Daher wurde ein Simulationsprogramm für Beugungseffekte entwickelt, welches aus den erstellten Maskenlayouts eine Topographie der Resistoberfläche ableitet und den Einfluss dieser Topographie auf die Abbildungstreue simuliert. Um die starre Zuordnung von Bausteinen zu Fertigungsprozessen, wie sie im Datenmodell des Baukastensystems verankert ist aufzuweichen, wurde nach einer Möglichkeit gesucht Fertigungstechnologien an Hand eines Kriteriensystems auswählbar zu machen. Es wird gezeigt, dass aus dem Maschinenbau bekannte Verfahren an die Belange der Mikrosystemtechnik angepasst werden können und so zur gezielten Auswahl geeigneter Technologien führen. Ein weiterer wichtiger Aspekt der Arbeit ist die Integration der einzelnen Module in eine geschlossene Entwicklungsumgebung. Hier wurde darauf geachtet, dass kommerzielle Werkzeuge mit den entwickelten Modulen über definierte Schnittstellen Daten austauschen und so ein geschlossenes System für den verhaltens- und fertigungsnahen Entwurf zur Verfügung steht. Der Entwickler wird über ein Projektplanungs und -management Werkzeug durch die einzelnen Entwurfsschritte geführt. Abschließend zeigen Anwendungsbeispiele verschiedene Aspekte des Systems. Am Beispiel einer doppelllagigen Mikrospule wird das Vorgehen beim Entwurf mittels Baukastensystem verdeutlicht. Diese Anwendung soll vor Allem detailliert die Arbeitsweise des Programms im Hinblick auf die Ableitung von Gesamtlayout und - prozesskette verdeutlichen. Des Weiteren wird hierbei ein Modul zum Grobentwurf von planaren Mikrospulen eingesetzt und die Anbindung an ein Finite Elemente Magnetics Programm vorgestellt. Ein zweites Anwendungsbeispiel verdeutlicht den Einsatz von Modulen zum Komponentenentwurf, falls für gewünschte Funktionen keine Bausteine im System vorgehalten werden. Die Membran eines Kraftsensors wird herangezogen, um die Vorgehensweise des Moduls zur Optimierung von Masken zu illustrieren. In der letzten Anwendung wird die Fähigkeit des Systems herausgestellt technologieübergreifende Bausteine zu einem neuen, komplexen Mikrosystem zusammenzuführen. Das Beispiel eines Mikrogreifers, der Komponenten aus der Siliziumtechnologie und der UV-Tiefenlithographie verbindet zeigt wie vorteilhaft die technologieübergreifende Entwicklung sein kann. Die Arbeit schließt mit einer Zusammenfassung und einem Ausblick für zukünftigen Forschungsbedarf ab.This work presents a method, which supports designers of microsystems. The main achievement of the system is that it supports the design of single components as well as the development of complex systems that consist of several different materials. In a first step available product development models are analyzed and the main challenges of MEMS design are discussed. This leads to the generation of a new process model for MEMS design that combines both behavioral modeling and productionrelated design. The system design forms the common starting point of the model. This process leads from the specifications to a function structure, which will than act as a basis for either the behavioral design path or the production-related design path. Both ways lead to a three-dimensional model of the proposed system, which can be used for further computational analysis. An analysis of the state-of-the-art in design tools for MEMS showed that most commonly the behavioral modeling is supported by such tools. All relevant methods neglect the design of process and mask layout for non-standard process flows. The area of building block systems mainly focuses on the definition of interfaces between single micro systems. This leads to the development of the presented system, which closes a gap in the area of component design. By means of building blocks on component level a new way of designing microsystems can be pointed out. The combination of layout and process design makes the reuse of once successfully fabricated elements possible. The system is presented as a software prototype and is attached to a central database. One important aspect of component design is the simulation of process steps. Especially high-aspect-ratio UV-lithographic patterning requires the use of a simulation tool for the estimation of diffraction effects during the exposure of complex three-dimensional structures. Different levels of microstructures and substrate cause diffraction effects during the exposure, which lead to a distortion of the original mask pattern. The presented simulation tool enables a designer to calculate intensity profiles on the resist surface and to estimate the impact of diffraction effects on the resulting resist pattern. An example is used to show the optimization of mask structures by adding special compensation structures. The presented building block system still lacks of flexibility regarding the use of evolving technologies. It uses fixed process sequences for single blocks to derive of process flow for the whole system. This leads to the fact that new fabrication processes have to be added to each block separately. To substitute single processes in a process chain a criterion system was developed to assist designers in decision making regarding the use of the best fabrication technology for a given design problem. Another important aspect is the integration of all tools into one single design environment. Here the fact that commercially available tools can communicate with other modules of the environment by especially designed interfaces was especially addressed. This ensures the consistent use of behavioral modeling and production-related design tools in one workflow. Different application examples show the capabilities of the presented system. The example of a spiral micro-coil is used to depict the use of the building block system. It focuses on the aspect of deriving a process flow and the layout. Additionally a module for the preliminary design of all coil dimensions and the interface to a finite-elementmagnetics tool is presented. In a second example the use of modules for the design of single components is shown. The membrane of a tactile force sensor acts as an example for deriving an optimized layout structure. The last application shows, how the system can handle blocks from different technologies to combine them into a complex microsystem. A hybrid micro gripper is used to depict how silicon based components can be combined with technologies from highaspect- ratio UV-lithography. The work concludes with a summary and a perspective for further research activities in this area

Algorithmic techniques for nanometer VLSI design and manufacturing closure

As Very Large Scale Integration (VLSI) technology moves to the nanoscale regime, design and manufacturing closure becomes very difficult to achieve due to increasing chip and power density. Imperfections due to process, voltage and temperature variations aggravate the problem. Uncertainty in electrical characteristic of individual device and wire may cause significant performance deviations or even functional failures. These impose tremendous challenges to the continuation of Moore's law as well as the growth of semiconductor industry. Efforts are needed in both deterministic design stage and variation-aware design stage. This research proposes various innovative algorithms to address both stages for obtaining a design with high frequency, low power and high robustness. For deterministic optimizations, new buffer insertion and gate sizing techniques are proposed. For variation-aware optimizations, new lithography-driven and post-silicon tuning-driven design techniques are proposed. For buffer insertion, a new slew buffering formulation is presented and is proved to be NP-hard. Despite this, a highly efficient algorithm which runs > 90x faster than the best alternatives is proposed. The algorithm is also extended to handle continuous buffer locations and blockages. For gate sizing, a new algorithm is proposed to handle discrete gate library in contrast to unrealistic continuous gate library assumed by most existing algorithms. Our approach is a continuous solution guided dynamic programming approach, which integrates the high solution quality of dynamic programming with the short runtime of rounding continuous solution. For lithography-driven optimization, the problem of cell placement considering manufacturability is studied. Three algorithms are proposed to handle cell flipping and relocation. They are based on dynamic programming and graph theoretic approaches, and can provide different tradeoff between variation reduction and wire- length increase. For post-silicon tuning-driven optimization, the problem of unified adaptivity optimization on logical and clock signal tuning is studied, which enables us to significantly save resources. The new algorithm is based on a novel linear programming formulation which is solved by an advanced robust linear programming technique. The continuous solution is then discretized using binary search accelerated dynamic programming, batch based optimization, and Latin Hypercube sampling based fast simulation

Regular cell design approach considering lithography-induced process variations

The deployment delays for EUVL, forces IC design to continue using 193nm wavelength lithography with innovative and costly techniques in order to faithfully print sub-wavelength features and combat lithography induced process variations. The effect of the lithography gap in current and upcoming technologies is to cause severe distortions due to optical diffraction in the printed patterns and thus degrading manufacturing yield. Therefore, a paradigm shift in layout design is mandatory towards more regular litho-friendly cell designs in order to improve line pattern resolution. However, it is still unclear the amount of layout regularity that can be introduced and how to measure the benefits and weaknesses of regular layouts. This dissertation is focused on searching the degree of layout regularity necessary to combat lithography variability and outperform the layout quality of a design. The main contributions that have been addressed to accomplish this objective are: (1) the definition of several layout design guidelines to mitigate lithography variability; (2) the proposal of a parametric yield estimation model to evaluate the lithography impact on layout design; (3) the development of a global Layout Quality Metric (LQM) including a Regularity Metric (RM) to capture the degree of layout regularity of a layout implementation and; (4) the creation of different layout architectures exploiting the benefits of layout regularity to outperform line-pattern resolution, referred as Adaptive Lithography Aware Regular Cell Designs (ALARCs). The first part of this thesis provides several regular layout design guidelines derived from lithography simulations so that several important lithography related variation sources are minimized. Moreover, a design level methodology, referred as gate biasing, is proposed to overcome systematic layout dependent variations, across-field variations and the non-rectilinear gate effect (NRG) applied to regular fabrics by properly configuring the drawn transistor channel length. The second part of this dissertation proposes a lithography yield estimation model to predict the amount of lithography distortion expected in a printed layout due to lithography hotspots with a reduced set of lithography simulations. An efficient lithography hotspot framework to identify the different layout pattern configurations, simplify them to ease the pattern analysis and classify them according to the lithography degradation predicted using lithography simulations is presented. The yield model is calibrated with delay measurements of a reduced set of identical test circuits implemented in a CMOS 40nm technology and thus actual silicon data is utilized to obtain a more realistic yield estimation. The third part of this thesis presents a configurable Layout Quality Metric (LQM) that considering several layout aspects provides a global evaluation of a layout design with a single score. The LQM can be leveraged by assigning different weights to each evaluation metric or by modifying the parameters under analysis. The LQM is here configured following two different set of partial metrics. Note that the LQM provides a regularity metric (RM) in order to capture the degree of layout regularity applied in a layout design. Lastly, this thesis presents different ALARC designs for a 40nm technology using different degrees of layout regularity and different area overheads. The quality of the gridded regular templates is demonstrated by automatically creating a library containing 266 cells including combinational and sequential cells and synthesizing several ITC'99 benchmark circuits. Note that the regular cell libraries only presents a 9\% area penalty compared to the 2D standard cell designs used for comparison and thus providing area competitive designs. The layout evaluation of benchmark circuits considering the LQM shows that regular layouts can outperform other 2D standard cell designs depending on the layout implementation.Los continuos retrasos en la implementación de la EUVL, fuerzan que el diseño de IC se realice mediante litografía de longitud de onda de 193 nm con innovadoras y costosas técnicas para poder combatir variaciones de proceso de litografía. La gran diferencia entre la longitud de onda y el tamaño de los patrones causa severas distorsiones debido a la difracción óptica en los patrones impresos y por lo tanto degradando el yield. En consecuencia, es necesario realizar un cambio en el diseño de layouts hacia diseños más regulares para poder mejorar la resolución de los patrones. Sin embargo, todavía no está claro el grado de regularidad que se debe introducir y como medir los beneficios y los perjuicios de los diseños regulares. El objetivo de esta tesis es buscar el grado de regularidad necesario para combatir las variaciones de litografía y mejorar la calidad del layout de un diseño. Las principales contribuciones para conseguirlo son: (1) la definición de diversas reglas de diseño de layout para mitigar las variaciones de litografía; (2) la propuesta de un modelo para estimar el yield paramétrico y así evaluar el impacto de la litografía en el diseño de layout; (3) el diseño de una métrica para analizar la calidad de un layout (LQM) incluyendo una métrica para capturar el grado de regularidad de un diseño (RM) y; (4) la creación de diferentes tipos de layout explotando los beneficios de la regularidad, referidos como Adaptative Lithography Aware Regular Cell Designs (ALARCs). La primera parte de la tesis, propone las diversas reglas de diseño para layouts regulares derivadas de simulaciones de litografía de tal manera que las fuentes de variación de litografía son minimizadas. Además, se propone una metodología de diseño para layouts regulares, referida como "gate biasing" para contrarrestar las variaciones sistemáticas dependientes del layout, las variaciones en la ventana de proceso del sistema litográfico y el efecto de puerta no rectilínea para configurar la longitud del canal del transistor correctamente. La segunda parte de la tesis, detalla el modelo de estimación del yield de litografía para predecir mediante un número reducido de simulaciones de litografía la cantidad de distorsión que se espera en un layout impreso debida a "hotspots". Se propone una eficiente metodología que identifica los distintos patrones de un layout, los simplifica para facilitar el análisis de los patrones y los clasifica en relación a la degradación predecida mediante simulaciones de litografía. El modelo de yield se calibra utilizando medidas de tiempo de un número reducido de idénticos circuitos de test implementados en una tecnología CMOS de 40nm y de esta manera, se utilizan datos de silicio para obtener una estimación realista del yield. La tercera parte de este trabajo, presenta una métrica para medir la calidad del layout (LQM), que considera diversos aspectos para dar una evaluación global de un diseño mediante un único valor. La LQM puede ajustarse mediante la asignación de diferentes pesos para cada métrica de evaluación o modificando los parámetros analizados. La LQM se configura mediante dos conjuntos de medidas diferentes. Además, ésta incluye una métrica de regularidad (RM) para capturar el grado de regularidad que se aplica en un diseño. Finalmente, esta disertación presenta los distintos diseños ALARC para una tecnología de 40nm utilizando diversos grados de regularidad y diferentes impactos en área. La calidad de estos diseños se demuestra creando automáticamente una librería de 266 celdas incluyendo celdas combinacionales y secuenciales y, sintetizando diversos circuitos ITC'99. Las librerías regulares solo presentan un 9% de impacto en área comparado con diseños de celdas estándar 2D y por tanto proponiendo diseños competitivos en área. La evaluación de los circuitos considerando la LQM muestra que los diseños regulares pueden mejorar otros diseños 2D dependiendo de la implementación del layout