Composition dependence of electronic structure and optical properties of Hf1-xSixOy gate dielectrics

Copyright © 2008 American Institute of Physics. This article is copyrighted as indicated in the article. Reuse of AIP content is subject to the terms at: http://scitation.aip.org/termsconditionsComposition-dependent electronic structure and optical properties of Hf1−xSixOy 0.1 x 0.6 gate dielectrics on Si at 450 °C grown by UV-photo-induced chemical vapor deposition UV-CVD have been investigated via x-ray photoemission spectroscopy and spectroscopy ellipsometry SE . By means of the chemical shifts in the Hf 4f, Si 2p, and O 1s spectra, the Hf–O–Si bondings in the as-deposited films have been confirmed. Analyses of composition-dependent band alignment of Hf1−xSixOy / Si gate stacks have shown that the valence band VB offset Ev demonstrates little change; however, the values of conduction band offset Ec increase with the increase in the silicon atomic composition, resulting from the increase in the separation between oxygen 2p orbital VB state and antibonding d states intermixed of Hf and Si. Analysis by SE, based on the Tauc–Lorentz model, has indicated that decreases in the optical dielectric constant and increase in band gap have been observed as a function of silicon contents. Changes in the complex dielectric functions and band gap Eg related to the silicon concentration in the films are discussed systematically. From the band offset and band gap viewpoint, these results suggest that Hf1−xSixOy films provide sufficient tunneling barriers for electrons and holes, making them promising candidates as alternative gate dielectrics.National Natural Science Foundation of China and Royal Society U.K

Thermal Stability of Neodymium Aluminates High- κ

Thin films of neodymium aluminate (NdAlOx) have been deposited by liquid injection metalorganic chemical vapor deposition (MOCVD) using the bimetallic alkoxide precursor [NdAl(OPri)6(PriOH)]2. The effects of high-temperature postdeposition annealing on NdAlOx thin films are reported. The as-deposited thin films are amorphous in nature. X-ray diffraction (XRD) and medium energy ion scattering (MEIS) show, respectively, no crystallization or interdiffusion of metal ions into the substrate after annealing at 950°C. The capacitance-voltage (C-V) and current-voltage (I-V) characteristics of the thin films exhibited good electrical integrity following annealing. The dielectric permittivity (κ) of the annealed NdAlOx was 12, and a density of interface states at flatband (Dit) of 4.01×1011  cm−2 eV−1 was measured. The deposited NdAlOx thin films are shown to be able to endure high-temperature stress and capable of maintaining excellent dielectric properties

Solution-Processed Metal Oxide Gate Dielectrics and Their Implementations in Zinc Oxide Based Thin Film Transistors

Thin-film transistors (TFTs) based on oxide semiconductors are a promising technology for a host of large-volume electronic applications. Whilst progress on solution-processed oxide semiconductors has been rapidly advancing, research efforts towards the development of new dielectrics has been relatively slow, with most of the reported work performed using conventional dielectrics based in SiO2. As a result, the majority of oxide transistors reported to date operate at relatively high voltages and hence consume significantly more power. In order to circumvent this bottleneck, recent work has been focussing on the development of low-voltage oxide transistors, including the use of high-k dielectrics, and several candidates have already been investigated and were mostly deposited by costly vacuum-based techniques. This thesis investigates the properties of high-k metal oxides dielectrics as well as their implementation in TFTs, deposited by spray pyrolysis, a simple and versatile technique that combines high yield and large area compatibility. In particular, the structural, optical, surface and electronic properties of tantalum aluminate (TaAlOx), hafnium titanate (HfTiO4) and zirconium silicate (ZrSiO4) were studied as along with their performance as gate dielectric for TFTs implementing ZnO semiconducting channels. In all cases, stochiometric TaAlOx, HfTiO4 and ZrSiO4 films deposited at < 550 °C were found to be amorphous with surface roughness of < 1 nm. The optical bandgap varies between 4.9 eV and 8.8 eV, 5.8 eV and 3.8 eV, and 5.8 eV and 8 eV for TaAlOx, HfTiO4 and ZrSiO4 films respectively. Their dielectric constant values vary between 24 and 7, 14 and 60, and 23 and 4.2 while their leakage current density at 1 MV/cm were between 10^-6 A/cm^2 and 10^-10 A/cm^2, 10^-7 A/cm^2 and 10 A/cm^2, and 10^-5 A/cm^2 and 10^-4 A/cm^2 respectively. Particularly, the stoichiometric TaAlOx, HfTiO4 and ZrSiO4 films exhibited the bandgap of 5.4 eV, 4.4 eV, 6.1 eV, dielectric constant of 13, 30, 12 and leakage current density at 1 MV/cm of 10^-8 A/cm^2, 0.3 A/cm^2, 10^-7 A/cm^2 respectively. The performance of ZnO – based TFTs employing stoichiometric TaAlOx, HfTiO4 and ZrSiO4 gate dielectric showed promising characteristics such as low voltage operation of 4 V, high electron mobility of 16 cm^2/Vs, 7 cm^2/Vs, 57 cm^2/Vs, high current modulation ratio of 10^5, 10^7, 10^6, low subthreshold swing of 0.56 V/dec, 0.17 V/dec, 0.28 V/dec, interface trap density of 7.7x10^12 cm^-2 ,2.1x10^12 cm^-2, 10^13 cm^-2 and threshold voltage of 3.2V, 0.6V, 0.1 V respectively. In addition, the effect of post-deposition annealing (at 800 °C for 30 mins in air) on HfTiO4 films were investigated. Stochiometric HfTiO4 films were crystalline of an orthorhombic structure, surface roughness of 1.95 nm, optical bandgap of 4.36 eV, dielectric constant of 38 and leakage current density of 5 mA/cm^2 at 1 MV/cm. These remarkable findings significantly demonstrated the achievement of a high- performance high-k metal oxide gate dielectrics as alternatives to the conventional SiO2 for future integration into wide areas of electronic application

Characterization of ultrathin gate dielectrics and multilayer charge injection barriers

Since the invention of the first integrated circuit, the semiconductor industry has distinguished itself by a phenomenally rapid pace of improvements in device performance. This trend of ever smaller and faster devices is a result of the ability to exponentially reduce feature sizes of integrated circuits, a trend commonly known as scaling . A reduction of overall feature sizes requires a simultaneous reduction in the thickness of the gate dielectric, SiO2, of a MOSFET. Gate oxides in the ultrathin regime (\u3c35 A) feature a large direct tunneling leakage current. The presence of this leakage current requires a reevaluation of standard characterization techniques as well as a reevaluation of the continued usefulness of SiO2 as the gate dielectric of choice for future applications. On the other hand, a thorough understanding of the dynamics of ultrathin oxides opens up a range of future device applications that were not possible with thicker oxides. Capacitance-voltage characterization has been the standard technique to study the electrical properties and interface quality of MOS devices. However, the presence of a large leakage current in ultrathin oxides distorts standard C-V measurements, rendering this technique no longer useful. In this work, a leakage compensated charge measurement is developed to overcome this difficulty. This technique produces static C-V curves, even for oxides as thin as 24 A, thereby permitting C-V characterization well into the direct tunneling regime. As an extension of this leakage problem, the usefulness of SiO2 as the gate dielectric of choice for future CMOS devices has been called into question. One solution - but not the only - calls for a new dielectric to replace SiO2 for future gate applications. This research presents some of the earliest results ever on the electrical properties of MOCVD and ALCVD hafnium oxides as a potential candidate. Electrical characterization revealed that the devices have characteristics such as large leakage currents, dielectric charging under stress, hysteresis and a large flatband voltage shift that is commonly found in materials such as the one that was investigated in this work. As one example of future device applications that become possible due to the scaling of ultrathin oxides, silicon-based multilayer charge injection barriers have been investigated. These barriers consist of alternating layers of ultrathin SiO2 and Si. The electrical properties of these structures were studied in detail and revealed that they can be used as an active tunnel dielectric in nonvolatile memory devices

Characterization and modeling of low-frequency noise in Hf-based high -kappa dielectrics for future cmos applications

The International Technology Roadmap for Semiconductors outlines the need for high-K dielectric based gate-oxide Metal Oxide Semiconductor Field Effect Transistors for sub-45 nm technology nodes. Gate oxides of hafnium seem to be the nearest and best alternative for silicon dioxide, when material, thermal and structural properties are considered. Usage of poly-Si as a gate electrode material degrades the performance of the device and hence gate stacks based on metal gate electrodes are gaining high interest. Though a substantial improvement in the performance has been achieved with these changes, reliability issues are a cause of concern. For analog and mixed-signal applications, low-frequency (I /f~ noise is a major reliability factor. Also in recent years. low frequency noise diagnostics has become a powerful tool for device performance and reliability characterization. This dissertation work demonstrates the necessity of gate stack engineering for achieving a low I/f noise performance. Changes in the material and process parameters of the devices, impact the 1/f noise behavior. The impact of 1/f noise on gate technology and processing parameters xvere identified and investigated. The thickness and the quality of the interfacial oxide, the nitridation effects of the layers, high-K oxide, bulk properties of the high-K layer. percentage of hafnium content in the high-K, post deposition anneal (PDA) treatments, effects of gate electrode material (poly-silicon. fully silicided or metal). Gate electrode processing are investigated in detail. The role of additional interfaces and bulk layers of the gate stack is understood. The dependence of low-frequency noise on high and low temperatures was also investigated. A systematic and a deeper understanding of these parameters on 1/f noise behavior are deduced which also forms the basis for improved physics-based 1/f noise modeling. The model considers the effect of the interfacial layer and also temperature, based on tunneling based thermally activated model. The simulation results of improved drain-current noise model agree well with the experimentally calculated values

Review and perspective of high-k dielectrics on silicon, Journal of Telecommunications and Information Technology, 2007, nr 2

The paper reviews recent work in the area of high-k dielectrics for application as the gate oxide in advanced MOSFETs. Following a review of relevant dielectric physics, we discuss challenges and issues relating to characterization of the dielectrics, which are compounded by electron trapping phenomena in the microsecond regime. Nearly all practical methods of preparation result in a thin interfacial layer generally of the form SiOx or a mixed oxide between Si and the high-k so that the extraction of the dielectric constant is complicated and values must be qualified by error analysis. The discussion is initially focussed on HfO2 but recognizing the propensity for crystallization of that material at modest temperatures, we discuss and review also, hafnia silicates and aluminates which have the potential for integration into a full CMOS process. The paper is concluded with a perspective on material contenders for the “end of road map” at the 22 nm node