Defective Behaviour of an 8T SRAM Cell with Open Defects

The defective behaviour of an 8T SRAM cell with open defects is analyzed. Full and resistive open defects have been considered in the electrical characterization of the defective cell. Due to the similarity between the classical 6T SRAM cell and the 8T cell, only defects affecting the read port transistors have been considered. In the work, it is shown how an open in a defective cell may influence the correct operation of a victim cell sharing the same read circuitry. Also, it is shown that the sequence of bits written on the defective cell prior to a read action can mask the presence of the defect. Different orders of critical resistance have been found depending on the location of the open defect. A 45nm technology has been used for the illustrative example presented in the wor

Development Of Test Platform Of Fpga Interconnect To Capture Marginal Open Defect

This research highlights the development of test platform of FPGA interconnect to capture marginal open defect on Altera® Stratix V devices. The need for at-speed test was due to the increasing number of marginal open defects, resulting from manufacturing process complexity anticipated from continuously shrinking transistors towards nanometer (nm) scale. The defect was unable to be captured by current stuck-at test and this research utilized the Launch on Shift (LOS) transition delay method to detect the marginal open defects. Towards the final implementation, there are few unique design implemented in order to generate the at-speed clocks and the pipelined scan enable signals to support LOS method. Meanwhile, the ability to test the interconnect on at-speed frequency required new routing tool control variables to limit the interconnect path lengths and device power consumption. The control variables are discussed further in this research. The LOS test patterns used in this research managed to cover up to 81% of the overall routing resources for marginal open defect effectively. Furthermore, the test was successfully implemented at frequencies up to 400 MHz and proven to be sensitive to routing delay to capture marginal open defects. The ability to capture the defect with only 0.56 kΩ resistance is better than the initial 3 kΩ target in this research. It is also better than other literatures which targeted between 6 kΩ to 10 kΩ only

Open topological defects and boundary RG flows

In the context of two-dimensional rational conformal field theories we consider topological junctions of topological defect lines with boundary conditions. We refer to such junctions as open topological defects. For a relevant boundary operator on a conformal boundary condition we consider a commutation relation with an open defect obtained by passing the junction point through the boundary operator. We show that when there is an open defect that commutes or anti-commutes with the boundary operator there are interesting implications for the boundary RG flows triggered by this operator. The end points of the flow must satisfy certain constraints which, in essence, require the end points to admit junctions with the same open defects. Furthermore, the open defects in the infrared must generate a subring under fusion that is isomorphic to the analogous subring of the original boundary condition. We illustrate these constraints by a number of explicit examples in Virasoro minimal models.Comment: 26 pages; v.2: section 3 rewritten and now includes a detailed discussion of RG counterterms, new example added at the end of section 4.2, extended discussion of the \psi_1,2 boundary flow in the Pentacritical model, minor improvements throughout the tex

Influence of parasitic capacitance variations on 65 nm and 32 nm predictive technology model SRAM core-cells

The continuous improving of CMOS technology allows the realization of digital circuits and in particular static random access memories that, compared with previous technologies, contain an impressive number of transistors. The use of new production processes introduces a set of parasitic effects that gain more and more importance with the scaling down of the technology. In particular, even small variations of parasitic capacitances in CMOS devices are expected to become an additional source of faulty behaviors in future technologies. This paper analyzes and compares the effect of parasitic capacitance variations in a SRAM memory circuit realized with 65 nm and 32 nm predictive technology model

Automating defects simulation and fault modeling for SRAMs

The continues improvement in manufacturing process density for very deep sub micron technologies constantly leads to new classes of defects in memory devices. Exploring the effect of fabrication defects in future technologies, and identifying new classes of realistic functional fault models with their corresponding test sequences, is a time consuming task up to now mainly performed by hand. This paper proposes a new approach to automate this procedure. The proposed method exploits the capabilities of evolutionary algorithms to automatically identify faulty behaviors into defective memories and to define the corresponding fault models and relevant test sequences. Target defects are modeled at the electrical level in order to optimize the results to the specific technology and memory architecture

Effect Analysis of Post Heating Temperature Variation on Metallography and Bending Test of GMAW ASTM A53 Steel Weld Joint

ASTM A53 steel is medium carbon steel with 0.3% carbon content and is often used for pipe manufacturing. The purpose of this study was to determine the effect of post heating temperature variation on bending and metallography test on weld joint of ASTM A53 steel using the GMAW process. The electrode used is ER-70S-6. Post heating temperature variations are 250oC, 300oC and 350oC. The bending test result showed that welding with 350oC postheating temperature produce the smallest open defect value. The microstructure result showed that welding with 350oC post heating temperature produce the smallest pearlite percentage in three areas observed

March CRF: an Efficient Test for Complex Read Faults in SRAM Memories

In this paper we study Complex Read Faults in SRAMs, a combination of various malfunctions that affect the read operation in nanoscale memories. All the memory elements involved in the read operation are studied, underlining the causes of the realistic faults concerning this operation. The requirements to cover these fault models are given. We show that the different causes of read failure are independent and may coexist in nanoscale SRAMs, summing their effects and provoking Complex Read Faults, CRFs. We show that the test methodology to cover this new read faults consists in test patterns that match the requirements to cover all the different simple read fault models. We propose a low complexity (?2N) test, March CRF, that covers effectively all the realistic Complex Read Fault

System, Circuit, And Method For Testing An Interconnect In A Multi-chip Substrate

A system for testing interconnects in multi-chip modules including a radio frequency resonator having a resonant circuit with a relatively high quality factor, the output of the resonant circuit being attached to a probe. Electrically coupled to the resonant circuit output is an apparatus to analyze the voltage signal output. The probe is applied to one end of an interconnect. When the probe is applied, the resonant frequency of the resonant circuit and the magnitude of the frequency response are altered due to the additional loading created by the interconnect. Due to the relatively high quality factor of the resonant circuit, the magnitude of the frequency response of the altered resonant circuit is measurably distinct from a predetermined reference magnitude at a predetermined reference frequency, thus indicating the existence of a defect. Additionally, the type of defect that exists is ascertainable by determining whether the resonant frequency of the altered resonant circuit is greater or less than the reference frequency by examining, for example, the phase response.Georgia Tech Research Corporatio

8T SRAM Defective Cell with Open Defects

The defective behaviour of an 8T SRAM cell with open defects is analyzed. Full and resistive open defects have been considered in the electrical characterization of the defective cell. Due to the similarity between the classical 6T SRAM cell and the 8T cell, only defects affecting the read port transistors have been considered. In the work, it is shown how an open in a defective cell may influence the correct operation of a victim cell sharing the same read circuitry. Also, it is shown that the sequence of bits written on the defective cell prior to a read action can mask the presence of the defect. Different orders of critical resistance have been found depending on the location of the open defect. A 45nm technology has been used for the illustrative example presented in the wor