41,539 research outputs found
A monolithic ASIC demonstrator for the Thin Time-of-Flight PET scanner
Time-of-flight measurement is an important advancement in PET scanners to
improve image reconstruction with a lower delivered radiation dose. This
article describes the monolithic ASIC for the TT-PET project, a novel idea for
a high-precision PET scanner for small animals. The chip uses a SiGe Bi-CMOS
process for timing measurements, integrating a fully-depleted pixel matrix with
a low-power BJT-based front-end per channel, integrated on the same 100 thick die. The target timing resolution is 30 ps RMS for electrons from the
conversion of 511 keV photons. A novel synchronization scheme using a
patent-pending TDC is used to allow the synchronization of 1.6 million channels
across almost 2000 different chips at picosecond-level. A full-featured
demonstrator chip with a 3x10 matrix of 500x500 pixels was
produced to validate each block. Its design and experimental results are
presented here
Product assurance technology for procuring reliable, radiation-hard, custom LSI/VLSI electronics
Advanced measurement methods using microelectronic test chips are described. These chips are intended to be used in acquiring the data needed to qualify Application Specific Integrated Circuits (ASIC's) for space use. Efforts were focused on developing the technology for obtaining custom IC's from CMOS/bulk silicon foundries. A series of test chips were developed: a parametric test strip, a fault chip, a set of reliability chips, and the CRRES (Combined Release and Radiation Effects Satellite) chip, a test circuit for monitoring space radiation effects. The technical accomplishments of the effort include: (1) development of a fault chip that contains a set of test structures used to evaluate the density of various process-induced defects; (2) development of new test structures and testing techniques for measuring gate-oxide capacitance, gate-overlap capacitance, and propagation delay; (3) development of a set of reliability chips that are used to evaluate failure mechanisms in CMOS/bulk: interconnect and contact electromigration and time-dependent dielectric breakdown; (4) development of MOSFET parameter extraction procedures for evaluating subthreshold characteristics; (5) evaluation of test chips and test strips on the second CRRES wafer run; (6) two dedicated fabrication runs for the CRRES chip flight parts; and (7) publication of two papers: one on the split-cross bridge resistor and another on asymmetrical SRAM (static random access memory) cells for single-event upset analysis
Phase Locked Loop Test Methodology
Phase locked loops are incorporated into almost every large-scale mixed signal and digital system on chip (SOC). Various types of PLL architectures exist including fully analogue, fully digital, semi-digital, and software based. Currently the most commonly used PLL architecture for SOC environments and chipset applications is the Charge-Pump (CP) semi-digital type. This architecture is commonly used for clock synthesis applications, such as the supply of a high frequency on-chip clock, which is derived from a low frequency board level clock. In addition, CP-PLL architectures are now frequently used for demanding RF (Radio Frequency) synthesis, and data synchronization applications. On chip system blocks that rely on correct PLL operation may include third party IP cores, ADCs, DACs and user defined logic (UDL). Basically, any on-chip function that requires a stable clock will be reliant on correct PLL operation. As a direct consequence it is essential that the PLL function is reliably verified during both the design and debug phase and through production testing. This chapter focuses on test approaches related to embedded CP-PLLs used for the purpose of clock generation for SOC. However, methods discussed will generally apply to CP-PLLs used for other applications
The Rolf of Test Chips in Coordinating Logic and Circuit Design and Layout Aids for VLSI
This paper emphasizes the need for multipurpose test chips and comprehensive procedures for use in supplying accurate input data to both logic and circuit simulators and chip layout aids. It is shown that the location of test structures within test chips is critical in obtaining representative data, because geometrical distortions introduced during the photomasking process can lead to
significant intrachip parameter variations. In order to transfer test chip designs quickly, accurately, and economically, a commonly accepted portable chip layout notation and commonly accepted parametric tester language are needed. In order to measure test chips more accurately and more rapidly, parametric testers with improved architecture need to be developed in conjunction with
innovative test structures with on-chip signal conditioning
A review of advances in pixel detectors for experiments with high rate and radiation
The Large Hadron Collider (LHC) experiments ATLAS and CMS have established
hybrid pixel detectors as the instrument of choice for particle tracking and
vertexing in high rate and radiation environments, as they operate close to the
LHC interaction points. With the High Luminosity-LHC upgrade now in sight, for
which the tracking detectors will be completely replaced, new generations of
pixel detectors are being devised. They have to address enormous challenges in
terms of data throughput and radiation levels, ionizing and non-ionizing, that
harm the sensing and readout parts of pixel detectors alike. Advances in
microelectronics and microprocessing technologies now enable large scale
detector designs with unprecedented performance in measurement precision (space
and time), radiation hard sensors and readout chips, hybridization techniques,
lightweight supports, and fully monolithic approaches to meet these challenges.
This paper reviews the world-wide effort on these developments.Comment: 84 pages with 46 figures. Review article.For submission to Rep. Prog.
Phy
EndoTOFPET-US a Novel Multimodal Tool for Endoscopy and Positron Emission Tomography
The EndoTOFPET-US project aims to jointly exploit Time-Of-Flight Positron
Emission Tomography (TOFPET) and ultrasound endoscopy with a multi-modal
instrument for the development of new biomarkers for pancreas and prostate
oncology. The paper outlines the functionality of the proposed instrument and
the challenges for its realization. The high level of miniaturization and
integration poses strong demands to the fields of scintillating
crystallography, ultra-fast photon detection, highly integrated electronics and
system integration. Solutions are presented to obtain a coincidence time
resolution better than 200 ps and a spatial resolution of ~1 mm with an
asymmetric TOFPET detector. A tracking system with better than 1 mm spatial
resolution precision enables the online alignment of the system. The detector
design, the production and test status of the single detecto
Product assurance technology for custom LSI/VLSI electronics
The technology for obtaining custom integrated circuits from CMOS-bulk silicon foundries using a universal set of layout rules is presented. The technical efforts were guided by the requirement to develop a 3 micron CMOS test chip for the Combined Release and Radiation Effects Satellite (CRRES). This chip contains both analog and digital circuits. The development employed all the elements required to obtain custom circuits from silicon foundries, including circuit design, foundry interfacing, circuit test, and circuit qualification
Efficiency and timing performance of the MuPix7 high-voltage monolithic active pixel sensor
The MuPix7 is a prototype high voltage monolithic active pixel sensor with
103 times 80 um2 pixels thinned to 64 um and incorporating the complete
read-out circuitry including a 1.25 Gbit/s differential data link. Using data
taken at the DESY electron test beam, we demonstrate an efficiency of 99.3% and
a time resolution of 14 ns. The efficiency and time resolution are studied with
sub-pixel resolution and reproduced in simulations.Comment: 7 pages, 13 figures, submitted to Nucl.Instr.Meth.
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