Modeling of a hardware VLSI placement system: Accelerating the Simulated Annealing algorithm

An essential step in the automation of electronic design is the placement of the physical components on the target semiconductor die. The placement step presents the opportunity to reduce costs in terms of wire length and performance degradation; however it is compute intensive and is NP-complete in terms of obtaining an optimal solution. As designs have grown in complexity and gate count, obtaining an optimal solution is not feasible due to time to market constraints or sheer compute effort required. Heuristic algorithms allow for efficient but sub-optimal designs to be produced with a reduction in processing time. A widely used algorithm is Simulated Annealing (SA). The goal of this work was to develop a model that would enable an analysis into the feasibility of developing a hardware accelerated placement system which uses SA at its core. The SA heuristic was analyzed for possible improvements in efficiency with focus given to targeting the system for hardware. A solution implementing parallel computing with specialized hardware configurations inside a field programmable gate array (FPGA) was investigated as having the possibility to improve the efficiency of the SA-based algorithm. All supporting subsystems were also described for a hardware accelerated model. A large speedup was analytically shown from both accelerating the critical path of the SA algorithm as well as novel methods of improving SA\u27s efficiency. As data throughput requirements were not included in this work, the results presented may be optimistic for an overall system speedup. However, the results clearly show that future work is warranted in studying the concept of a hardware accelerated placement system

3D Global Router: a Study to Optimize Congestion, Wirelength and Via for Circuit Layout

The increasing size of integrated circuits and aggressive shrinking process feature size for IC manufacturing process poses signicant challenges on traditional physical design problems. Various design rules signicantly complicate the physical design problems and large problem size abides nothing but extremely e cient techniques. Leading physical design tools have to be powerful enough to handle complex design demands and be nimble enough to waste no runtime. This thesis studies the challenges faced by global routing problem, one of the traditional physical design problems that needs to be pushed to its new limit. This work proposes three e ective tools to tackle congestion, wire and via optimization in global routing process, from three di erent aspects. The number of vias generated during the global routing stage is a critical factor for the yield of integrated circuits. However, most global routers only approach the problem by charging a cost for vias in the maze routing cost function. The first work of this thesis, FastRoute 4.0 presents a global router that addresses the via number optimization problem throughout the entire global routing ow. It introduces the via aware Steiner tree generation, 3-bend routing and layer assignment with careful ordering to reduce via count. The integration of these three techniques with existing academic global routers achieves signicant reduction in via count without any sacrice in runtime. Despite of the recent development for popular rip-up and reroute framework, the congestion elimination process remains arbitrary and requires signicant tuning. Global routing has congestion elimination as the first and foremost priority and congestion issue becomes increasingly severe due to timing requirements, design for manufacturability. The second work of this thesis, an auction algorithm based pre-processing framework (APF) for global routing focuses on how to eliminate congestion e ectively. In order to achieve more consistent congestion elimination, the framework uses auction based detour techniques to alleviate the impacts of greedy sequential manner of maze routing, which remains as a major drawback in the most popular global routing framework. In the framework, APF first identies the most congested global routing locations by an interval over ow lower bound technique. Then APF uses auction based detour algorithm to compute which nets to detour and where to detour. The framework can be applied to any global routers and would help them to achieve signicant improvement in both solution quality and runtime. The third work in this thesis combines the advantage of the two framework used to minimize via usage in global routing: 3D routers with good solution quality and e cient 2D routers with layer assignment process. It results in a new multi-level 3D global router called MGR (multi-level global router) that combines the advantage of both kinds. MGR resorts to an e cient multi-level framework to reroute nets in the congested region on the 3D grid graph. Routing on the coarsened grid graph speeds up the global router while 3D routing introduces less vias. The powerful multi-level rerouting framework wraps three innovative routing techniques together: an adaptive resource reservation technique in coarsening process, a new 3-terminal maze routing algorithm and a network flow based solution propagation method in uncoarsening process. As a result, MGR can achieve the solution quality close to 3D routers with comparable runtime of 2D routers

Algorithmic techniques for physical design : macro placement and under-the-cell routing

With the increase of chip component density and new manufacturability constraints imposed by modern technology nodes, the role of algorithms for electronic design automation is key to the successful implementation of integrated circuits. Two of the critical steps in the physical design flows are macro placement and ensuring all design rules are honored after timing closure. This thesis proposes contributions to help in these stages, easing time-consuming manual steps and helping physical design engineers to obtain better layouts in reduced turnaround time. The first contribution is under-the-cell routing, a proposal to systematically connect standard cell components via lateral pins in the lower metal layers. The aim is to reduce congestion in the upper metal layers caused by extra metal and vias, decreasing the number of design rule violations. To allow cells to connect by abutment, a standard cell library is enriched with instances containing lateral pins in a pre-selected sharing track. Algorithms are proposed to maximize the numbers of connections via lateral connection by mapping placed cell instances to layouts with lateral pins, and proposing local placement modifications to increase the opportunities for such connections. Experimental results show a significant decrease in the number of pins, vias, and in number of design rule violations, with negligible impact on wirelength and timing. The second contribution, done in collaboration with eSilicon (a leading ASIC design company), is the creation of HiDaP, a macro placement tool for modern industrial designs. The proposed approach follows a multilevel scheme to floorplan hierarchical blocks, composed of macros and standard cells. By exploiting RTL information available in the netlist, the dataflow affinity between these blocks is modeled and minimized to find a macro placement with good wirelength and timing properties. The approach is further extended to allow additional engineer input, such as preferred macro locations, and also spectral and force methods to guide the floorplanning search. Experimental results show that the layouts generated by HiDaP outperforms those obtained by a state-of-the-art EDA physical design software, with similar wirelength and better timing when compared to manually designed tape-out ready macro placements. Layouts obtained by HiDaP have successfully been brought to near timing closure with one to two rounds of small modifications by physical design engineers. HiDaP has been fully integrated in the design flows of the company and its development remains an ongoing effort.A causa de l'increment de la densitat de components en els xip i les noves restriccions de disseny imposades pels últims nodes de fabricació, el rol de l'algorísmia en l'automatització del disseny electrònic ha esdevingut clau per poder implementar circuits integrats. Dos dels passos crucials en el procés de disseny físic és el placement de macros i assegurar la correcció de les regles de disseny un cop les restriccions de timing del circuit són satisfetes. Aquesta tesi proposa contribucions per ajudar en aquests dos reptes, facilitant laboriosos passos manuals en el procés i ajudant als enginyers de disseny físic a obtenir millors resultats en menys temps. La primera contribució és el routing "under-the-cell", una proposta per connectar cel·les estàndard usant pins laterals en les capes de metall inferior de manera sistemàtica. L'objectiu és reduir la congestió en les capes de metall superior causades per l'ús de metall i vies, i així disminuir el nombre de violacions de regles de disseny. Per permetre la connexió lateral de cel·les, estenem una llibreria de cel·les estàndard amb dissenys que incorporen connexions laterals. També proposem modificacions locals al placement per permetre explotar aquest tipus de connexions més sovint. Els resultats experimentals mostren una reducció significativa en el nombre de pins, vies i nombre de violacions de regles de disseny, amb un impacte negligible en wirelength i timing. La segona contribució, desenvolupada en col·laboració amb eSilicon (una empresa capdavantera en disseny ASIC), és el desenvolupament de HiDaP, una eina de macro placement per a dissenys industrials actuals. La proposta segueix un procés multinivell per fer el floorplan de blocks jeràrquics, formats per macros i cel·les estàndard. Mitjançant la informació RTL disponible en la netlist, l'afinitat de dataflow entre els mòduls es modela i minimitza per trobar macro placements amb bones propietats de wirelength i timing. La proposta també incorpora la possibilitat de rebre input addicional de l'enginyer, com ara suggeriments de les posicions de les macros. Finalment, també usa mètodes espectrals i de forçes per guiar la cerca de floorplans. Els resultats experimentals mostren que els dissenys generats amb HiDaP són millors que els obtinguts per eines comercials capdavanteres de EDA. Els resultats també mostren que els dissenys presentats poden obtenir un wirelength similar i millor timing que macro placements obtinguts manualment, usats per fabricació. Alguns dissenys obtinguts per HiDaP s'han dut fins a timing-closure en una o dues rondes de modificacions incrementals per part d'enginyers de disseny físic. L'eina s'ha integrat en el procés de disseny de eSilicon i el seu desenvolupament continua més enllà de les aportacions a aquesta tesi.Postprint (published version

Algorithmic techniques for physical design : macro placement and under-the-cell routing

With the increase of chip component density and new manufacturability constraints imposed by modern technology nodes, the role of algorithms for electronic design automation is key to the successful implementation of integrated circuits. Two of the critical steps in the physical design flows are macro placement and ensuring all design rules are honored after timing closure. This thesis proposes contributions to help in these stages, easing time-consuming manual steps and helping physical design engineers to obtain better layouts in reduced turnaround time. The first contribution is under-the-cell routing, a proposal to systematically connect standard cell components via lateral pins in the lower metal layers. The aim is to reduce congestion in the upper metal layers caused by extra metal and vias, decreasing the number of design rule violations. To allow cells to connect by abutment, a standard cell library is enriched with instances containing lateral pins in a pre-selected sharing track. Algorithms are proposed to maximize the numbers of connections via lateral connection by mapping placed cell instances to layouts with lateral pins, and proposing local placement modifications to increase the opportunities for such connections. Experimental results show a significant decrease in the number of pins, vias, and in number of design rule violations, with negligible impact on wirelength and timing. The second contribution, done in collaboration with eSilicon (a leading ASIC design company), is the creation of HiDaP, a macro placement tool for modern industrial designs. The proposed approach follows a multilevel scheme to floorplan hierarchical blocks, composed of macros and standard cells. By exploiting RTL information available in the netlist, the dataflow affinity between these blocks is modeled and minimized to find a macro placement with good wirelength and timing properties. The approach is further extended to allow additional engineer input, such as preferred macro locations, and also spectral and force methods to guide the floorplanning search. Experimental results show that the layouts generated by HiDaP outperforms those obtained by a state-of-the-art EDA physical design software, with similar wirelength and better timing when compared to manually designed tape-out ready macro placements. Layouts obtained by HiDaP have successfully been brought to near timing closure with one to two rounds of small modifications by physical design engineers. HiDaP has been fully integrated in the design flows of the company and its development remains an ongoing effort.A causa de l'increment de la densitat de components en els xip i les noves restriccions de disseny imposades pels últims nodes de fabricació, el rol de l'algorísmia en l'automatització del disseny electrònic ha esdevingut clau per poder implementar circuits integrats. Dos dels passos crucials en el procés de disseny físic és el placement de macros i assegurar la correcció de les regles de disseny un cop les restriccions de timing del circuit són satisfetes. Aquesta tesi proposa contribucions per ajudar en aquests dos reptes, facilitant laboriosos passos manuals en el procés i ajudant als enginyers de disseny físic a obtenir millors resultats en menys temps. La primera contribució és el routing "under-the-cell", una proposta per connectar cel·les estàndard usant pins laterals en les capes de metall inferior de manera sistemàtica. L'objectiu és reduir la congestió en les capes de metall superior causades per l'ús de metall i vies, i així disminuir el nombre de violacions de regles de disseny. Per permetre la connexió lateral de cel·les, estenem una llibreria de cel·les estàndard amb dissenys que incorporen connexions laterals. També proposem modificacions locals al placement per permetre explotar aquest tipus de connexions més sovint. Els resultats experimentals mostren una reducció significativa en el nombre de pins, vies i nombre de violacions de regles de disseny, amb un impacte negligible en wirelength i timing. La segona contribució, desenvolupada en col·laboració amb eSilicon (una empresa capdavantera en disseny ASIC), és el desenvolupament de HiDaP, una eina de macro placement per a dissenys industrials actuals. La proposta segueix un procés multinivell per fer el floorplan de blocks jeràrquics, formats per macros i cel·les estàndard. Mitjançant la informació RTL disponible en la netlist, l'afinitat de dataflow entre els mòduls es modela i minimitza per trobar macro placements amb bones propietats de wirelength i timing. La proposta també incorpora la possibilitat de rebre input addicional de l'enginyer, com ara suggeriments de les posicions de les macros. Finalment, també usa mètodes espectrals i de forçes per guiar la cerca de floorplans. Els resultats experimentals mostren que els dissenys generats amb HiDaP són millors que els obtinguts per eines comercials capdavanteres de EDA. Els resultats també mostren que els dissenys presentats poden obtenir un wirelength similar i millor timing que macro placements obtinguts manualment, usats per fabricació. Alguns dissenys obtinguts per HiDaP s'han dut fins a timing-closure en una o dues rondes de modificacions incrementals per part d'enginyers de disseny físic. L'eina s'ha integrat en el procés de disseny de eSilicon i el seu desenvolupament continua més enllà de les aportacions a aquesta tesi

A framework for fine-grain synthesis optimization of operational amplifiers

This thesis presents a cell-level framework for Operational Amplifiers Synthesis (OASYN) coupling both circuit design and layout. For circuit design, the tool applies a corner-driven optimization, accounting for on-chip performance variations. By exploring the process, voltage, and temperature variations space, the tool extracts design worst case solution. The tool undergoes sensitivity analysis along with Pareto-optimality to achieve required specifications. For layout phase, OASYN generates a DRC proved automated layout based on a sized circuit-level description. Morata et al. (1996) introduced an elegant representation of block placement called sequence pair for general floorplans (SP). Like TCG and BSG, but unlike O-tree, B*tree, and CBL, SP is P-admissible. Unlike SP, TCG supports incremental update during operation and keeps the information of the boundary modules as well as their relative positions in the representation. Block placement algorithms that are based on SP use heuristic optimization algorithms, e.g., simulated annealing where generation of large number of sequence pairs are required. Therefore a fast algorithm is needed to generate sequence pairs after each solution perturbation. The thesis presents a new simple and efficient O(n) runtime algorithm for fast realization of incremental update for cost evaluation. The algorithm integrates sequence pair and transitive closure graph advantages into TCG-S* a superior topology update scheme which facilitates the search for optimum desired floorplan. Experiments show that TCG-S* is better than existing works in terms of area utilization and convergence speed. Routing-aware placement is implemented in OASYN, handling symmetry constraints, e.g., interdigitization, common centroid, along with congestion elimination and the enhancement of placement routability

Interconnect-driven floorplanning.

Sham Chiu Wing.Thesis (M.Phil.)--Chinese University of Hong Kong, 2002.Includes bibliographical references (leaves 107-113).Abstracts in English and Chinese.Chapter 1 --- Introduction --- p.1Chapter 1.1 --- Motivations --- p.1Chapter 1.2 --- Progress on the Problem --- p.2Chapter 1.3 --- Our Contributions --- p.3Chapter 1.4 --- Thesis Organization --- p.5Chapter 2 --- Preliminaries --- p.6Chapter 2.1 --- Introduction --- p.6Chapter 2.1.1 --- The Role of Floorplanning --- p.6Chapter 2.1.2 --- Wirelength Estimation --- p.7Chapter 2.1.3 --- Different Types of Floorplan --- p.8Chapter 2.2 --- Representations of Floorplan --- p.10Chapter 2.2.1 --- Polish Expressions --- p.10Chapter 2.2.2 --- Sequence Pair --- p.11Chapter 2.2.3 --- Bounded-Sliceline Grid (BSG) Structure --- p.13Chapter 2.2.4 --- O-Tree --- p.14Chapter 2.2.5 --- B*-Tree --- p.16Chapter 2.2.6 --- Corner Block List --- p.18Chapter 2.2.7 --- Twin Binary Tree --- p.19Chapter 2.2.8 --- Comparisons between Different Representations --- p.20Chapter 2.3 --- Algorithms of Floorplan Design --- p.20Chapter 2.3.1 --- Constraint Based Floorplanning --- p.21Chapter 2.3.2 --- Integer Programming Based Floorplanning --- p.21Chapter 2.3.3 --- Neural Learning Based Floorplanning --- p.22Chapter 2.3.4 --- Rectangular Dualization --- p.22Chapter 2.3.5 --- Simulated Annealing --- p.23Chapter 2.3.6 --- Genetic Algorithm --- p.23Chapter 2.4 --- Summary --- p.24Chapter 3 --- Literature Review on Interconnect-Driven Floorplanning --- p.25Chapter 3.1 --- Introduction --- p.25Chapter 3.2 --- Simulated Annealing Approach --- p.25Chapter 3.2.1 --- """Pepper - A Timing Driven Early Floorplanner""" --- p.25Chapter 3.2.2 --- """A Timing Driven Block Placer Based on Sequence Pair Model""" --- p.26Chapter 3.2.3 --- """Integrated Floorplanning and Interconnect Planning""" --- p.27Chapter 3.2.4 --- """Interconnect Driven Floorplanning with Fast Global Wiring Planning and Optimization""" --- p.27Chapter 3.3 --- Genetic Algorithm Approach --- p.28Chapter 3.3.1 --- "“Timing Influenced General-cell Genetic Floorplanning""" --- p.28Chapter 3.4 --- Force Directed Approach --- p.29Chapter 3.4.1 --- """Timing Influenced Force Directed Floorplanning""" --- p.29Chapter 3.5 --- Congestion Planning --- p.30Chapter 3.5.1 --- """On the Behavior of Congestion Minimization During Placement""" --- p.30Chapter 3.5.2 --- """Congestion Minimization During Placement""" --- p.31Chapter 3.5.3 --- "“Estimating Routing Congestion Using Probabilistic Anal- ysis""" --- p.31Chapter 3.6 --- Buffer Planning --- p.32Chapter 3.6.1 --- """Buffer Block Planning for Interconnect Driven Floor- planning""" --- p.32Chapter 3.6.2 --- """Routability Driven Repeater Block Planning for Interconnect- centric Floorplanning""" --- p.33Chapter 3.6.3 --- """Provably Good Global Buffering Using an Available Block Plan""" --- p.34Chapter 3.6.4 --- "“Planning Buffer Locations by Network Flows""" --- p.34Chapter 3.6.5 --- """A Practical Methodology for Early Buffer and Wire Re- source Allocation""" --- p.35Chapter 3.7 --- Summary --- p.36Chapter 4 --- Floorplanner with Fixed Buffer Planning [34] --- p.37Chapter 4.1 --- Introduction --- p.37Chapter 4.2 --- Overview of the Floorplanner --- p.38Chapter 4.3 --- Congestion Model --- p.38Chapter 4.3.1 --- Construction of Grid Structure --- p.39Chapter 4.3.2 --- Counting the Number of Routes at a Grid --- p.40Chapter 4.3.3 --- Buffer Location Computation --- p.41Chapter 4.3.4 --- Counting Routes with Blocked Grids --- p.42Chapter 4.3.5 --- Computing the Probability of Net Crossing --- p.43Chapter 4.4 --- Time Complexity --- p.44Chapter 4.5 --- Simulated Annealing --- p.45Chapter 4.6 --- Wirelength Estimation --- p.46Chapter 4.6.1 --- Center-to-center Estimation --- p.47Chapter 4.6.2 --- Corner-to-corner Estimation --- p.47Chapter 4.6.3 --- Intersection-to-intersection Estimation --- p.48Chapter 4.7 --- Multi-pin Nets Handling --- p.49Chapter 4.8 --- Experimental Results --- p.50Chapter 4.9 --- Summary --- p.51Chapter 5 --- Floorplanner with Flexible Buffer Planning [35] --- p.53Chapter 5.1 --- Introduction --- p.53Chapter 5.2 --- Overview of the Floorplanner --- p.54Chapter 5.3 --- Congestion Model --- p.55Chapter 5.3.1 --- Probabilistic Model with Variable Interval Buffer Inser- tion Constraint --- p.57Chapter 5.3.2 --- Time Complexity --- p.61Chapter 5.4 --- Buffer Planning --- p.62Chapter 5.4.1 --- Estimation of Buffer Usage --- p.62Chapter 5.4.2 --- Estimation of Buffer Resources --- p.69Chapter 5.5 --- Two-phases Simulated Annealing --- p.70Chapter 5.6 --- Wirelength Estimation --- p.72Chapter 5.7 --- Multi-pin Nets Handling --- p.73Chapter 5.8 --- Experimental Results --- p.73Chapter 5.9 --- Remarks --- p.76Chapter 5.10 --- Summary --- p.76Chapter 6 --- Global Router --- p.77Chapter 6.1 --- Introduction --- p.77Chapter 6.2 --- Overview of the Global Router --- p.77Chapter 6.3 --- Buffer Insertion Constraint and Congestion Constraint --- p.78Chapter 6.4 --- Multi-pin Nets Handling --- p.79Chapter 6.5 --- Routing Methodology --- p.79Chapter 6.6 --- Implementation --- p.80Chapter 6.7 --- Summary --- p.86Chapter 7 --- Interconnect-Driven Floorplanning by Alternative Packings --- p.87Chapter 7.1 --- Introduction --- p.87Chapter 7.2 --- Overview of the Method --- p.87Chapter 7.3 --- Searching Alternative Packings --- p.89Chapter 7.3.1 --- Rectangular Supermodules in Sequence Pair --- p.89Chapter 7.3.2 --- Finding rearrangable module sets --- p.90Chapter 7.3.3 --- Alternative Sequence Pairs --- p.94Chapter 7.4 --- Implementation --- p.97Chapter 7.4.1 --- Re-calculation of Interconnect Cost --- p.98Chapter 7.4.2 --- Cost Function --- p.101Chapter 7.4.3 --- Time Complexity --- p.101Chapter 7.5 --- Experimental Results --- p.101Chapter 7.6 --- Summary --- p.103Chapter 8 --- Conclusion --- p.105Bibliography --- p.10

Algorithmic techniques for nanometer VLSI design and manufacturing closure

As Very Large Scale Integration (VLSI) technology moves to the nanoscale regime, design and manufacturing closure becomes very difficult to achieve due to increasing chip and power density. Imperfections due to process, voltage and temperature variations aggravate the problem. Uncertainty in electrical characteristic of individual device and wire may cause significant performance deviations or even functional failures. These impose tremendous challenges to the continuation of Moore's law as well as the growth of semiconductor industry. Efforts are needed in both deterministic design stage and variation-aware design stage. This research proposes various innovative algorithms to address both stages for obtaining a design with high frequency, low power and high robustness. For deterministic optimizations, new buffer insertion and gate sizing techniques are proposed. For variation-aware optimizations, new lithography-driven and post-silicon tuning-driven design techniques are proposed. For buffer insertion, a new slew buffering formulation is presented and is proved to be NP-hard. Despite this, a highly efficient algorithm which runs > 90x faster than the best alternatives is proposed. The algorithm is also extended to handle continuous buffer locations and blockages. For gate sizing, a new algorithm is proposed to handle discrete gate library in contrast to unrealistic continuous gate library assumed by most existing algorithms. Our approach is a continuous solution guided dynamic programming approach, which integrates the high solution quality of dynamic programming with the short runtime of rounding continuous solution. For lithography-driven optimization, the problem of cell placement considering manufacturability is studied. Three algorithms are proposed to handle cell flipping and relocation. They are based on dynamic programming and graph theoretic approaches, and can provide different tradeoff between variation reduction and wire- length increase. For post-silicon tuning-driven optimization, the problem of unified adaptivity optimization on logical and clock signal tuning is studied, which enables us to significantly save resources. The new algorithm is based on a novel linear programming formulation which is solved by an advanced robust linear programming technique. The continuous solution is then discretized using binary search accelerated dynamic programming, batch based optimization, and Latin Hypercube sampling based fast simulation

Placement techniques in automatic analog layout generation.

模擬電路版圖設計是一個非常複雜和耗時的過程。通常情況下，設計一個高質量的模擬電路版圖需要電子工程師花費幾週甚至更長的時間。模擬電路的電子特性對於電路的細節設計非常敏感，因此，減小電路中的失配現象成為模擬電路版圖設計中一個非常重要的課題。在本論文中，我們提出了一系列實際的佈局技術，來降低電路的失配並提高繞線的成功率。我們可以非常容易的將這些技術整合至一個完整的模擬佈局和佈線的工具中，此工具可以在幾分鐘內生成一個完整的、高質量的模擬電路版圖。同時，該版圖能夠通過設計規則驗證（DRC）和佈局與電路設計一致性檢測（LVS）。模擬結果顯示，它的電路性能能夠與達到甚至超出手工設計的電路版圖。我們的論文主要作出了以下兩方面貢獻。1. 平衡佈局：對於模擬電路中的電子元器件，如電容、電阻、晶體管等進行一維和二維的平衡佈局。電子工程師可以根據不同的設計需求，通過選擇不同的佈局參數來改變電路的佈局排列方式。同時，在模擬退火算法中，我們著重考慮了器件間的匹配以生成高質量的模擬電路佈局。2. 消除阻塞的電路佈局：在模擬電路設計中，我們期望盡量避免在電子元器件密度較高的區域進行繞線。因此，我們需要在電路佈局設計過程中在電子元器件間留有足夠的佈線空間。為達到這個目標，我們提出了更精確的阻塞估計方法和版圖拓展方法，使其能夠生成一個高質量、高繞線成功率的電路佈局結果。為了驗證生成的電路版圖的質量和匹配特性，我們利用蒙地卡羅方法來模擬電路中的製程偏差和失配特性。實驗結果顯示，我們的工具可以在幾分鐘內自動生成高質量的電路版圖，與人工設計通常需要花費數日至數週相比，設計時間大幅縮短，同時電路的匹配特性得以提升。Analog layout design is a complicated and time-consuming process. It often takes couples of weeks for the layout designers to generate a qualied layout. The elec-trical properties of analog circuit are very sensitive to the layout details, and mis-match reduction becomes a very important issue in analog layout design.In this thesis, we will present some practical placement techniques to reduce mismatch and improve routability. These techniques can be easily integrated into a complete analog placement and routing ow, which can produce in just a few min-utes a complete and high quality layout for analog circuits that passes the design rule check, layout-schematic check and with performance veried by simulations. The contents of this thesis will focus on the following two issues:(1) Symmetry Placement: We consider symmetric placement of transistors, re-sistors and capacitors, which includes 1-D symmetry and 2-D symmetry (or called common centroid). Different symmetric placement congurations, derived accord-ing to the practical needs in analog design, are considered for the matching devices in the simulated annealing engine of the placer in order to generate a placement with high quality.(2) Congestion-driven Placement: In analog design, wires are preferred not be routed over active devices, so we need to leave enough spaces properly for routing between the devices during the placement process. To achieve this, we explore congestion estimation and layout expansion during the placement step in order to produce a good and routable solution.In order to verify the quality of the generated layouts in terms of mismatch, we will run Monte Carlo simulations on them with variations in process and mismatch. Experiments show that our methodology can generate high quality layout automatically in just a few minutes while manual design may take couples of days.Detailed summary in vernacular field only.Detailed summary in vernacular field only.Detailed summary in vernacular field only.Detailed summary in vernacular field only.Detailed summary in vernacular field only.Cui, Guxin.Thesis (M.Phil.)--Chinese University of Hong Kong, 2012.Abstracts also in Chinese.Abstract --- p.iAcknowledgement --- p.ivChapter 1 --- Introduction --- p.1Chapter 1.1 --- Background --- p.1Chapter 1.2 --- Physical Design --- p.2Chapter 1.3 --- Analog Placement --- p.4Chapter 1.3.1 --- Methodologies of Analog Placement --- p.4Chapter 1.3.2 --- Symmetry Constraints of Analog Placement --- p.5Chapter 1.4 --- Process Variation and Layout Mismatch --- p.6Chapter 1.4.1 --- Process Variation --- p.6Chapter 1.4.2 --- Random Mismatch and Systematic Mismatch --- p.7Chapter 1.5 --- Monte Carlo Simulation Procedure --- p.9Chapter 1.6 --- Problem Formulation of Placement --- p.9Chapter 1.7 --- Motivations --- p.10Chapter 1.8 --- Contributions --- p.11Chapter 1.9 --- Thesis Organization --- p.12Chapter 2 --- Literature Review on Analog Placement --- p.13Chapter 2.1 --- Topological Representations Handling Symmetry Constraints --- p.14Chapter 2.1.1 --- Symmetry within the Sequence-Pair (SP) Representation . --- p.14Chapter 2.1.2 --- Block Placement with Symmetry Constraints Based on the O-Tree Non-Slicing Representation --- p.16Chapter 2.1.3 --- Placement with Symmetry Constraints for Analog Layout Design Using TCG-S --- p.17Chapter 2.1.4 --- Modeling Non-Slicing Floorplans with Binary Trees --- p.19Chapter 2.1.5 --- Segment Trees Handle Symmetry Constraints --- p.20Chapter 2.1.6 --- Center-based Corner Block List --- p.22Chapter 2.2 --- Other Works on Analog Placement Constraints --- p.25Chapter 2.2.1 --- Deterministic Analog Placement with Hierarchically Bounded Enumeration and Enhanced Shape Functions --- p.25Chapter 2.2.2 --- Analog Placement Based on Symmetry-Island Formulation --- p.27Chapter 2.2.3 --- Heterogeneous B*-Trees for Analog Placement with Symmetry and Regularity Considerations --- p.28Chapter 2.3 --- Summary --- p.31Chapter 3 --- Common-Centroid Analog Placement --- p.32Chapter 3.1 --- Problem Formulation --- p.33Chapter 3.2 --- Overview of Our Work --- p.35Chapter 3.3 --- Handling Common Centroid Constraints in Different Devices --- p.37Chapter 3.3.1 --- Common Centroid Placement of Resistors --- p.38Chapter 3.3.2 --- Common Centroid Placement of Transistors --- p.44Chapter 3.3.3 --- Common Centroid Placement of Capacitors --- p.47Chapter 3.4 --- Congestion Estimation and Layout Expansion --- p.50Chapter 3.4.1 --- Blockage-Aware Congestion Estimation --- p.51Chapter 3.4.2 --- Layout Expansion --- p.56Chapter 3.5 --- Simulated Annealing --- p.59Chapter 3.5.1 --- Types of Moves --- p.59Chapter 3.5.2 --- Handling Devices in Symmetry Group --- p.59Chapter 3.5.3 --- Cost Function of Simulated Annealing --- p.61Chapter 3.6 --- Summary --- p.62Chapter 4 --- Experimental Results and Monte-Carlo Simulations --- p.64Chapter 4.1 --- Study of Congestion-driven Layout Expansion --- p.64Chapter 4.2 --- Monte Carlo Simulations --- p.70Chapter 4.2.1 --- Devices Modeling --- p.70Chapter 4.2.2 --- Study of Layouts with and without Symmetry Groups --- p.71Chapter 4.2.3 --- Study of Layouts with and without Self-Symmetry Devices --- p.73Chapter 4.2.4 --- Study of Layouts with Different Number of Symmetry Groups --- p.74Chapter 4.2.5 --- Study of Large and Small Size Capacitors Array --- p.76Chapter 4.3 --- Comparison of Automatic and Manual Layouts using Monte Carlo Simulations --- p.79Chapter 5 --- Conclusion --- p.86Bibliography --- p.8