On the performance of digital adaptive spur cancellation for multi-standard radio frequency transceivers

15 pagesInternational audienceThis study deals with the asymptotic performance of a multiple-spur cancellation scheme. Radio frequency transceivers are now multi-standard and specific impairment can occur. The clock harmonics, called spurs, can leak into the signal band of the reception stage, and thus degrade the performance. The performance of a fully digital approach is presented here. A one-spur cancellation scheme is first described, for which we exploit the a priori knowledge of the spur frequency to create a reference of the polluting tone with the same frequency. A least-mean-square (LMS) algorithm block that uses this reference to mitigate the polluter is designed. However, due to imperfections in the physical components, there is a shift between the a priori frequency and the actual frequency of the spur, and the spur is affected by Brownian phase noise. Under these circumstances, we study the asymptotic and transient performance of the algorithm. We next improve the transient performance by adding a previously proposed adaptive-step-size process. In a second part of this paper, we present a multiple-spur parallel approach that is based on the one-spur cancellation scheme, for which we provide a closed-form expression of the asymptotic signal-plus-noise interference ratio in the presence of frequency shifts and phase noise

Reduced-complexity Digital Predistortion in Flexible Radio Spectrum Access

Wireless communications is nowadays seen as one of the main foundations of technological advancements in, e.g., healthcare, education, agriculture, transportation, computing, personal communications, media, and entertainment. This requires major technological developments and advances at different levels of the wireless communication systems and networks. In particular, it is required to utilize the currently available frequency spectrum in a more and more efficient way, while also adopting new spectral bands. Moreover, it is required that cheaper and smaller electronic components are used to build future wireless communication systems to facilitate increasingly cost-effective solutions. Meanwhile, energy efficiency becomes extremely important in wide scale deployments of the networks both from a running cost point of view, and from an environmental impact point of view. This is the big picture, or the so called ‘bird’s eye view’ of the challenges that are yet to be met in this very interesting and fast developing field of science.The power amplifier (PA) is the most power-hungry component in most RF transmitters. Consequently, its energy efficiency significantly contributes to the overall energy efficiency of the transmitter, and in fact the whole wireless network. Unfortunately, energy efficiency enhancement implies operating the PA closer to its saturation region, which typically results in severe nonlinear distortion that can deteriorate the signal quality and cause interference to neighboring users, both of which negatively impact the system spectral efficiency. Moreover, in flexible spectrum access scenarios, which are essential for improving the spectral efficiency, particular in the form of non-contiguous radio spectrum access, the nonlinear distortion due to the PA becomes even more severe and can significantly impact the overall network performance. For example, in noncontiguous carrier aggregation (CA) in LTE-Advanced, it has been demonstrated that in addition to the classical in-band distortion and regrowth around the main carriers, harmful spurious emission components are generated which can easily violate the spurious emission limits even in the case of user equipment (UE) transmitters.Technological advances in the digital electronics domain have enabled us to approach this problem from a digital signal processing point of view in the form of widely-adopted and researched digital predistortion (DPD) technology. However, when the signal bandwidth gets larger, and flexible or non-contiguous spectrum access is introduced, the complexity of the DPD increases and the power consumed in the digital domain by the DPD itself becomes higher and higher, to the extent that it might be close to, or even surpass, the energy savings achieved from using a more efficient PA. The problem becomes even more challenging at the UE side which has relatively limited computational capabilities and lower transmit power. This dilemma can be resolved by developing novel reduced-complexity DPD solutions in such flexible spectrum access and/or wide bandwidth scenarios while not sacrificing the DPD performance, which is the main topic area that this thesis work contributes to.The first contribution of this thesis is the development of a spur-injection based sub-band DPD structure for spurious emission mitigation in noncontiguous transmission scenarios. A novel and effective learning algorithm is also introduced, for the proposed sub-band DPD, based on the decorrelation principle. Mathematical models of the unwanted emissions are formulated based on realistic PA models with memory, followed by developing an efficient DPD structure for mitigating these emissions with reducedcomplexity in both the DPD main processing and learning paths while providing excellent spurious emission suppression. In the special case when the spurious emissions overlap with the own RX band in frequency division duplexing (FDD) transceivers, a novel subband DPD solution is also developed that uses the main RX for DPD learning without requiring any additional observation RX, thus further reducing the DPD complexity.The second contribution is the development of a novel reduced-complexity concurrent DPD, with a single-feedback receiver path, for carrier aggregation-like scenarios. The proposed solution is based on a simple and flexible DPD structure with decorrelationbased parameter learning. Practical simulations and RF measurements demonstrate that the proposed concurrent DPD provides excellent linearization performance, in terms of in-band error vector magnitude (EVM) and adjacent channel leakage ratio (ACLR), when compared to state-of-the-art concurrent DPD solutions, despite its reduced computational complexity in both the DPD main path processing and parameter learning.The third contribution is the development of a new and novel frequency-optimized DPD solution which can tailor its linearization capabilities to any particular regions of the spectrum. Detailed mathematical expressions of the power spectrum at the PA output as a function of the DPD coefficients are formulated. A Newton-Raphson optimization routine is then utilized to optimize the suppression of unwanted emissions at arbitrary pre-specified frequencies at the PA output. From a complexity reduction perspective, this means that for a given linearization performance at a particular frequency range, an optimized and reduced-complexity DPD can be used.Detailed quantitative complexity analysis, of all the proposed DPD solutions, is performed in this thesis. The complexity and linearization performance are also compared to state-of-the-art DPD solutions in the literature to validate and demonstrate the complexity reduction aspect without sacrificing the linearization performance. Moreover, all the DPD solutions developed in this thesis are tested in practical RF environments using real cellular power amplifiers that are commercially used in the latest wireless communication systems, both at the base station side and at the mobile terminal side. These experiments, along with the strong theoretical foundation of the developed DPD solutions prove that they can be commercially used as such to enhance the performance, energy efficiency, and cost effectiveness of next generation wireless transmitters

High-speed Time-interleaved Digital-to-Analog Converter (TI-DAC) for Self-Interference Cancellation Applications

Nowadays, the need for higher data-rate is constantly growing to enhance the quality of the daily communication services. The full-duplex (FD) communication is exemplary method doubling the data-rate compared to half-duplex one. However, part of the strong output signal of the transmitter interferes to the receiver-side because they share the same antenna with limited attenuation and, as a result, the receiver’s performance is corrupted. Hence, it is critical to remove the leakage signal from the receiver’s path by designing another block called self-interference cancellation (SIC). The main goal of this dissertation is to develop the SIC block embedded in the current-mode FD receivers. To this end, the regenerated cancellation current signal is fed to the inputs of the base-band filter and after the mixer of a (direct-conversion) current-mode FD receiver. Since the pattern of the transmitter (the digital signal generated by DSP) is known, a high-speed digital-to-Analog converter (DAC) with medium-resolution can perfectly suppress main part of the leakage on the receiver path. A capacitive DAC (CDAC) is chosen among the available solutions because it is compatible with advanced CMOS technology for high-speed application and the medium-resolution designs. Although the main application of the design is to perform the cancellation, it can also be employed as a stand-alone DAC in the Analog (I/Q) transmitter. The SIC circuitry includes a trans-impedance amplifier (TIA), two DACs, high-speed digital circuits, and built-in-self-test section (BIST). According to the available specification for full-duplex communication system, the resolution and working frequency of the CDAC are calculated (designed) equal to 10-bit (3 binary+ 2 binary + 5 thermometric) and 1GHz, respectively. In order to relax the design of the TIA (settling time of the DAC), the CDAC implements using 2-way time-interleaved (TI) manner (the effective SIC frequency equals 2GHz) without using any calibration technique. The CDAC is also developed with the split-capacitor technique to lower the negative effects of the conventional binary-weighted DAC. By adding one extra capacitor on the left-side of the split-capacitor, LSB-side, the value of the split-capacitor can be chosen as an integer value of the unit capacitor. As a result, it largely enhances the linearity of the CADC and cancellation performance. If the block works as a stand-alone DAC with non-TI mode, the digital input code representing a Sinus waveform with an amplitude 1dB less than full-scale and output frequency around 10.74MHz, chosen by coherent sampling rule, then the ENOB, SINAD, SFDR, and output signal are 9.4-bit, 58.2 dB, 68.4dBc, and -9dBV. The simulated value of the |DNL| (static linearity) is also less than 0.7. The similar simulation was done in the SIC mode while the capacitive-array woks in the TI mode and cancellation current is set to the full-scale. Hence, the amount of cancelling the SI signal at the output of the TIA, SNDR, SFDR, SNDRequ. equals 51.3dB, 15.1 dB, 24dBc, 66.4 dB. The designed SIC cannot work as a closed-loop design. The layout was optimally drawn in order to minimize non-linearity, the power-consumption of the decoders, and reduce the complexity of the DAC. By distributing the thermometric cells across the array and using symmetrical switching scheme, the DAC is less subjected to the linear and gradient effect of the oxide. Based on the post-layout simulation results, the deviation of the design after drawing the layout is studied. To compare the results of the schematic and post-layout designs, the exact conditions of simulation above (schematic simulations) are used. When the block works as a stand-alone CDAC, the ENOB, SINAD, SFDR are 8.5-bit, 52.6 dB, 61.3 dBc. The simulated value of the |DNL| (static linearity) is also limited to 1.3. Likewise, the SI signal at the output of the TIA, SNDR, SFDR, SNDRequ. are equal to 44dB, 11.7 dB, 19 dBc, 55.7 dB

Digital enhancement techniques for fractional-N frequency synthesizers

Meeting the demand for unprecedented connectivity in the era of internet-of-things (IoT) requires extremely energy efficient operation of IoT nodes to extend battery life. Managing the data traffic generated by trillions of such nodes also puts severe energy constraints on the data centers. Clock generators that are essential elements in these systems consume significant power and therefore must be optimized for low power and high performance. The focus of this thesis is on improving the energy efficiency of frequency synthesizers and clocking modules by exploring design techniques at both the architectural and circuit levels. In the first part of this work, a digital fractional-N phase locked loop (FNPLL) that employs a high resolution time-to-digital converter (TDC) and a truly ΔΣ fractional divider to achieve low in-band noise with a wide bandwidth is presented. The fractional divider employs a digital-to-time converter (DTC) to cancel out ΔΣ quantization noise in time domain, thus alleviating TDC dynamic range requirements. The proposed digital architecture adopts a narrow range low-power time-amplifier based TDC (TA-TDC) to achieve sub 1ps resolution. Fabricated in 65nm CMOS process, the prototype PLL achieves better than -106dBc/Hz in-band noise and 3MHz PLL bandwidth at 4.5GHz output frequency using 50MHz reference. The PLL achieves excellent jitter performance of 490fsrms, while consumes only 3.7mW. This translates to the best reported jitter-power figure-of-merit (FoM) of -240.5dB among previously reported FNPLLs. Phase noise performance of ring oscillator based digital FNPLLs is severely compromised by conflicting bandwidth requirements to simultaneously suppress oscillator phase and quantization noise introduced by the TDC, ΔΣ fractional divider, and digital-to-analog converter (DAC). As a consequence, their FoM that quantifies the power-jitter tradeoff is at least 25dB worse than their LC-oscillator based FNPLL counterparts. In the second part of this thesis, we seek to close this performance gap by extending PLL bandwidth using quantization noise cancellation techniques and by employing a dual-path digital loop filter to suppress the detrimental impact of DAC quantization noise. A prototype was implemented in a 65nm CMOS process operating over a wide frequency range of 2.0GHz-5.5GHz using a modified extended range multi-modulus divider with seamless switching. The proposed digital FNPLL achieves 1.9psrms integrated jitter while consuming only 4mW at 5GHz output. The measured in-band phase noise is better than -96 dBc/Hz at 1MHz offset. The proposed FNPLL achieves wide bandwidth up to 6MHz using a 50 MHz reference and its FoM is -228.5dB, which is at about 20dB better than previously reported ring-based digital FNPLLs. In the third part, we propose a new multi-output clock generator architecture using open loop fractional dividers for system-on-chip (SoC) platforms. Modern multi-core processors use per core clocking, where each core runs at its own speed. The core frequency can be changed dynamically to optimize for performance or power dissipation using a dynamic frequency scaling (DFS) technique. Fast frequency switching is highly desirable as long as it does not interrupt code execution; therefore it requires smooth frequency transitions with no undershoots. The second main requirement in processor clocking is the capability of spread spectrum frequency modulation. By spreading the clock energy across a wide bandwidth, the electromagnetic interference (EMI) is dramatically reduced. A conventional PLL clock generation approach suffers from a slow frequency settling and limited spread spectrum modulation capabilities. The proposed open loop fractional divider architecture overcomes the bandwidth limitation in fractional-N PLLs. The fractional divider switches the output frequency instantaneously and provides an excellent spread spectrum performance, where precise and programmable modulation depth and frequency can be applied to satisfy different EMI requirements. The fractional divider has unlimited modulation bandwidth resulting in spread spectrum modulation with no filtering, unlike fractional-N PLL; consequently it achieves higher EMI reduction. A prototype fractional divider was implemented in a 65nm CMOS process, where the measured peak-to-peak jitter is less than 27ps over a wide frequency range from 20MHz to 1GHz. The total power consumption is about 3.2mW for 1GHz output frequency. The all-digital implementation of the divider occupies the smallest area of 0.017mm2 compared to state-of-the-art designs. As the data rate of serial links goes higher, the jitter requirements of the clock generator become more stringent. Improving the jitter performance of conventional PLLs to less than (200fsrms) always comes with a large power penalty (tens of mWs). This is due to the PLL coupled noise bandwidth trade-off, which imposes stringent noise requirements on the oscillator and/or loop components. Alternatively, an injection-locked clock multiplier (ILCM) provides many advantages in terms of phase noise, power, and area compared to classical PLLs, but they suffer from a narrow lock-in range and a high sensitivity to PVT variations especially at a large multiplication factor (N). In the fourth part of this thesis, a low-jitter, low-power LC-based ILCM with a digital frequency-tracking loop (FTL) is presented. The proposed FTL relies on a new pulse gating technique to continuously tune the oscillator's free-running frequency. The FTL ensures robust operation across PVT variations and resolves the race condition existing in injection locked PLLs by decoupling frequency tuning from the injection path. As a result, the phase locking condition is only determined by the injection path. This work also introduces an accurate theoretical large-signal analysis for phase domain response (PDR) of injection locked oscillators (ILOs). The proposed PDR analysis captures the asymmetric nature of ILO's lock-in range, and the impact of frequency error on injection strength and phase noise performance. The proposed architecture and analysis are demonstrated by a prototype fabricated in 65 nm CMOS process with active area of 0.25mm2. The prototype ILCM multiplies the reference frequency by 64 to generate an output clock in the range of 6.75GHz-8.25GHz. A superior jitter performance of 190fsrms is achieved, while consuming only 2.25mW power. This translates to a best FoM of -251dB. Unlike conventional PLLs, ILCMs have been fundamentally limited to only integer-N operation and cannot synthesize fractional-N frequencies. In the last part of this thesis, we extend the merits of ILCMs to fractional-N and overcome this fundamental limitation. We employ DTC-based QNC techniques in order to align injected pulses to the oscillator's zero crossings, which enables it to pull the oscillator toward phase lock, thus realizing a fractional-N ILCM. Fabricated in 65nm CMOS process, a prototype 20-bit fractional-N ILCM with an output range of 6.75GHz-8.25GHz consumes only 3.25mW. It achieves excellent jitter performance of 110fsrms and 175fsrms in integer- and fractional-N modes respectively, which translates to the best-reported FoM in both integer- (-255dB) and fractional-N (-252dB) modes. The proposed fractional-N ILCM also features the first-reported rapid on/off capability, where the transient absolute jitter performance at wake-up is bounded below 4ps after less than 4ns. This demonstrates almost instantaneous phase settling. This unique capability enables tremendous energy saving by turning on the clock multiplier only when needed. This energy proportional operation leverages idle times to save power at the system-level of wireline and wireless transceivers

Software-Defined Radio Demonstrators: An Example and Future Trends

Software-defined radio requires the combination of software-based signal processing and the enabling hardware components. In this paper, we present an overview of the criteria for such platforms and the current state of development and future trends in this area. This paper will also provide details of a high-performance flexible radio platform called the maynooth adaptable radio system (MARS) that was developed to explore the use of software-defined radio concepts in the provision of infrastructure elements in a telecommunications application, such as mobile phone basestations or multimedia broadcasters

Integrated Filters and Couplers for Next Generation Wireless Tranceivers

The main focus of this thesis is to investigate the critical nonlinear distortion issues affecting RF/Microwave components such as power amplifiers (PA) and develop new and improved solutions that will improve efficiency and linearity of next generation RF/Microwave mobile wireless communication systems. This research involves evaluating the nonlinear distortions in PA for different analog and digital signals which have been a major concern. The second harmonic injection technique is explored and used to effectively suppress nonlinear distortions. This method consists of simultaneously feeding back the second harmonics at the output of the power amplifier (PA) into the input of the PA. Simulated and measured results show improved linearity results. However, for increasing frequency bandwidth, the suppression abilities reduced which is a limitation for 4G LTE and 5G networks that require larger bandwidth (above 5 MHz). This thesis explores creative ways to deal with this major drawback. The injection technique was modified with the aid of a well-designed band-stop filter. The compact narrowband notch filter designed was able to suppress nonlinear distortions very effectively when used before the PA. The notch filter is also integrated in the injection technique for LTE carrier aggregation (CA) with multiple carriers and significant improvement in nonlinear distortion performance was observed. This thesis also considers maximizing efficiency alongside with improved linearity performance. To improve on the efficiency performance of the PA, the balanced PA configuration was investigated. However, another major challenge was that the couplers used in this configuration are very large in size at the desired operating frequency. In this thesis, this problem was solved by designing a compact branch line coupler. The novel coupler was simulated, fabricated and measured with performance comparable to its conventional equivalent and the coupler achieved substantial size reduction over others. The coupler is implemented in the balanced PA configuration giving improved input and output matching abilities. The proposed balanced PA is also implemented in 4G LTE and 5G wireless transmitters. This thesis provides simulation and measured results for all balanced PA cases with substantial efficiency and linearity improvements observed even for higher bandwidths (above 5 MHz). Additionally, the coupler is successfully integrated with rectifiers for improved energy harvesting performance and gave improved RF-dc conversion efficienc

Méthodes de traitement numérique du signal pour l'annulation d'auto-interférences dans un terminal mobile

Radio frequency transceivers are now massively multi-standards, which meansthat several communication standards can cohabit in the same environment. As a consequence,analog components have to face critical design constraints to match the differentstandards requirements and self-interferences that are directly introduced by the architectureitself are more and more present and detrimental. This work exploits the dirty RFparadigm : we accept the signal to be polluted by self-interferences and we develop digitalsignal processing algorithms to mitigate those aforementioned pollutions and improve signalquality. We study here different self-interferences and propose baseband models anddigital adaptive algorithms for which we derive closed form formulae of both transientand asymptotic performance. We also propose an original adaptive step-size overlay toimprove transient performance of our method. We finally validate our approach on a systemon chip dedicated to cellular communications and on a software defined radio.Les émetteurs-récepteurs actuels tendent à devenir multi-standards c’est-àdireque plusieurs standards de communication peuvent cohabiter sur la même puce. Lespuces sont donc amenées à traiter des signaux de formes très différentes, et les composantsanalogiques subissent des contraintes de conception de plus en plus fortes associées au supportdes différentes normes. Les auto-interférences, c’est à dire les interférences généréespar le système lui-même, sont donc de plus en plus présentes, et de plus en plus problématiquesdans les architectures actuelles. Ces travaux s’inscrivent dans le paradigmede la « radio sale » qui consiste à accepter une pollution partielle du signal d’intérêtet à réaliser, par l’intermédiaire d’algorithmes, une atténuation de l’impact de ces pollutionsauto-générées. Dans ce manuscrit, on s’intéresse à différentes auto-interférences(phénomène de "spurs", de "Tx leakage", ...) dont on étudie les modèles numériques etpour lesquelles nous proposons des stratégies de compensation. Les algorithmes proposéssont des algorithmes de traitement du signal adaptatif qui peuvent être vus comme des« algorithmes de soustraction de bruit » basés sur des références plus ou moins précises.Nous dérivons analytiquement les performances transitionnelles et asymptotiques théoriquesdes algorithmes proposés. On se propose également d’ajouter à nos systèmes unesur-couche originale qui permet d’accélérer la convergence, tout en maintenant des performancesasymptotiques prédictibles et paramétrables. Nous validons enfin notre approchesur une puce dédiée aux communications cellulaires ainsi que sur une plateforme de radiologicielle