14 research outputs found

    Picosecond Multilevel Resistive Switching in Tantalum Oxide Thin Films

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    The increasing demand for high-density data storage leads to an increasing interest in novel memory concepts with high scalability and the opportunity of storing multiple bits in one cell. A promising candidate is the redox-based resistive switch repositing the information in form of different resistance states. For reliable programming, the underlying physical parameters need to be understood. We reveal that the programmable resistance states are linked to internal series resistances and the fundamental nonlinear switching kinetics. The switching kinetics of Ta2_{2}O5_{5}-based cells was investigated in a wide range over 15 orders of magnitude from 250 ps to 105^{5} s. We found strong evidence for a switching speed of 10 ps which is consistent with analog electronic circuit simulations. On all time scales, multi-bit data storage capabilities were demonstrated. The elucidated link between fundamental material properties and multi-bit data storage paves the way for designing resistive switches for memory and neuromorphic applications.Comment: Compiled PDF should contain 24 pages, 5 figures and 50 reference

    Resistive switching devices with improved control of oxygen vacancies dynamics

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    L'abstract è presente nell'allegato / the abstract is in the attachmen

    Fabrication, Characterization and Integration of Resistive Random Access Memories

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    The functionalities and performances of today's computing systems are increasingly dependent on the memory block. This phenomenon, also referred as the Von Neumann bottleneck, is the main motivation for the research on memory technologies. Despite CMOS technology has been improved in the last 50 years by continually increasing the device density, today's mainstream memories, such as SRAM, DRAM and Flash, are facing fundamental limitations to continue this trend. These memory technologies, based on charge storage mechanisms, are suffering from the easy loss of the stored state for devices scaled below 10 nm. This results in a degradation of the performance, reliability and noise margin. The main motivation for the development of emerging non volatile memories is the study of a different mechanism to store the digital state in order to overcome this challenge. Among these emerging technologies, one of the strongest candidate is Resistive Random Access Memory (ReRAM), which relies on the formation or rupture of a conductive filament inside a dielectric layer. This thesis focuses on the fabrication, characterization and integration of ReRAM devices. The main subject is the qualitative and quantitative description of the main factors that influence the resistive memory electrical behavior. Such factors can be related either to the memory fabrication or to the test environment. The first category includes variations in the fabrication process steps, in the device geometry or composition. We discuss the effect of each variation, and we use the obtained database to gather insights on the ReRAM working mechanism and the adopted methodology by using statistical methods. The second category describes how differences in the electrical stimuli sent to the device change the memory performances. We show how these factors can influence the memory resistance states, and we propose an empirical model to describe such changes. We also discuss how it is possible to control the resistance states by modulating the number of input pulses applied to the device. In the second part of this work, we present the integration of the fabricated devices in a CMOS technology environment. We discuss a Verilog-A model used to simulate the device characteristics, and we show two solutions to limit the sneak-path currents for ReRAM crossbars: a dedicated read circuit and the development of selector devices. We describe the selector fabrication, as well as the electrical characterization and the combination with our ReRAMs in a 1S1R configuration. Finally, we show two methods to integrate ReRAM devices in the BEoL of CMOS chips

    A Contribution Towards Intelligent Autonomous Sensors Based on Perovskite Solar Cells and Ta2O5/ZnO Thin Film Transistors

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    Many broad applications in the field of robotics, brain-machine interfaces, cognitive computing, image and speech processing and wearables require edge devices with very constrained power and hardware requirements that are challenging to realize. This is because these applications require sub-conscious awareness and require to be always “on”, especially when integrated with a sensor node that detects an event in the environment. Present day edge intelligent devices are typically based on hybrid CMOS-memristor arrays that have been so far designed for fast switching, typically in the range of nanoseconds, low energy consumption (typically in nano-Joules), high density and endurance (exceeding 1015 cycles). On the other hand, sensory-processing systems that have the same time constants and dynamics as their input signals, are best placed to learn or extract information from them. To meet this requirement, many applications are implemented using external “delay” in the memristor, in a process which enables each synapse to be modeled as a combination of a temporal delay and a spatial weight parameter. This thesis demonstrates a synaptic thin film transistor capable of inherent logic functions as well as compute-in-memory on similar time scales as biological events. Even beyond a conventional crossbar array architecture, we have relied on new concepts in reservoir computing to demonstrate a delay system reservoir with the highest learning efficiency of 95% reported to date, in comparison to equivalent two terminal memristors, using a single device for the task of image processing. The crux of our findings relied on enhancing our capability to model the unique physics of the device, in the scope of the current thesis, that is not amenable to conventional TCAD simulations. The model provides new insight into the redox characteristics of the gate current and paves way for assessment of device performance in compute-in-memory applications. The diffusion-based mechanism of the device, effectively enables time constants that have potential in applications such as gesture recognition and detection of cardiac arrythmia. The thesis also reports a new orientation of a solution processed perovskite solar cell with an efficiency of 14.9% that is easily integrable into an intelligent sensor node. We examine the influence of the growth orientation on film morphology and solar cell efficiency. Collectively, our work aids the development of more energy-efficient, powerful edge-computing sensor systems for upcoming applications of the IOT

    2022 roadmap on neuromorphic computing and engineering

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    Modern computation based on von Neumann architecture is now a mature cutting-edge science. In the von Neumann architecture, processing and memory units are implemented as separate blocks interchanging data intensively and continuously. This data transfer is responsible for a large part of the power consumption. The next generation computer technology is expected to solve problems at the exascale with 1018^{18} calculations each second. Even though these future computers will be incredibly powerful, if they are based on von Neumann type architectures, they will consume between 20 and 30 megawatts of power and will not have intrinsic physically built-in capabilities to learn or deal with complex data as our brain does. These needs can be addressed by neuromorphic computing systems which are inspired by the biological concepts of the human brain. This new generation of computers has the potential to be used for the storage and processing of large amounts of digital information with much lower power consumption than conventional processors. Among their potential future applications, an important niche is moving the control from data centers to edge devices. The aim of this roadmap is to present a snapshot of the present state of neuromorphic technology and provide an opinion on the challenges and opportunities that the future holds in the major areas of neuromorphic technology, namely materials, devices, neuromorphic circuits, neuromorphic algorithms, applications, and ethics. The roadmap is a collection of perspectives where leading researchers in the neuromorphic community provide their own view about the current state and the future challenges for each research area. We hope that this roadmap will be a useful resource by providing a concise yet comprehensive introduction to readers outside this field, for those who are just entering the field, as well as providing future perspectives for those who are well established in the neuromorphic computing community

    An In Situ Study Of Resistance Degradation And Switching Of Bulk Yttria-Stabilized Zirconia And Strontium Titanate Single Crystals

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    Understanding resistance changes under a constant or set of bipolar-switching voltage(s) is important for thin-film devices, specifically multilayer capacitors and resistance-switching memory. However, identifying critical locations of changes and failures in thin films is difficult, so this work studies the same phenomena in single crystals of yttria-stabilized zirconia (YSZ) and iron-doped strontium titanate (STO) starting with highly accelerated lifetime tests (HALT) at higher temperatures. Although doped STO is a p-type semiconductor and YSZ a fast oxygen-ion conductor with little electronic conductivity, their DC resistance-degradation curves are remarkably indistinguishable. Yet different mechanisms were revealed by in-situ hot-stage photography and thermal imaging in two test environments—air and silicone oil. In YSZ, DC (electro)reduction does not appreciably alter oxygen stoichiometry; nevertheless, above a threshold voltage, it can raise the chemical potential of electrons to the conduction-band level, thereby triggering a metal-insulator (resistance) transition. In contrast, DC-stressed STO undergoes oxygen-vacancy demixing, forming a p-n junction with elevated electronic conductivity, albeit late-stage-demixing can be so sluggish that the steady state is difficult to reach in low-temperature HALT. In both oxides, an inherent instability in the governing field equation dictates degradation follows filament-like paths, which explains the strong field dependence and large variation of lifetimes. Upon further voltage reversals, degraded crystals exhibit different, large resistance changes. In YSZ, a change in DC voltage can already cause a resistance change, which is unipolar switching. But additional resistance degradation after voltage reversal can facilitate filament fragmentation, thus rendering the crystal bipolarly switchable due to a voltage-sensitive metal-insulator transition in a thin layer of barely metallic YSZ adjacent to the original anode. In STO, voltage reversals broaden/narrow a nanolayer of stoichiometric, ionic STO (called i-region) that straddles the p-n junction, by driving electromigration to act in-concert/against back-diffusion of oxygen ions. Thickening/thinning of such region leads to resistance increase/decrease, resulting in the so-called eightwise” bipolar switching. (Interface-controlled, “counter-eightwise” switching was also observed in more severely degraded STO.) As these phenomena find analogies in thin-film devices, mechanisms revealed above have provided new insight that will help understand and improve the performance and reliability of engineering devices

    Avalanches and the edge-of-chaos in neuromorphic nanowire networks

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    The brain's efficient information processing is enabled by the interplay between its neuro-synaptic elements and complex network structure. This work reports on the neuromorphic dynamics of nanowire networks (NWNs), a brain-inspired system with synapse-like memristive junctions embedded within a recurrent neural network-like structure. Simulation and experiment elucidate how collective memristive switching gives rise to long-range transport pathways, drastically altering the network's global state via a discontinuous phase transition. The spatio-temporal properties of switching dynamics are found to be consistent with avalanches displaying power-law size and life-time distributions, with exponents obeying the crackling noise relationship, thus satisfying criteria for criticality. Furthermore, NWNs adaptively respond to time varying stimuli, exhibiting diverse dynamics tunable from order to chaos. Dynamical states at the edge-of-chaos are found to optimise information processing for increasingly complex learning tasks. Overall, these results reveal a rich repertoire of emergent, collective dynamics in NWNs which may be harnessed in novel, brain-inspired computing approaches

    Electronic Nanodevices

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    The start of high-volume production of field-effect transistors with a feature size below 100 nm at the end of the 20th century signaled the transition from microelectronics to nanoelectronics. Since then, downscaling in the semiconductor industry has continued until the recent development of sub-10 nm technologies. The new phenomena and issues as well as the technological challenges of the fabrication and manipulation at the nanoscale have spurred an intense theoretical and experimental research activity. New device structures, operating principles, materials, and measurement techniques have emerged, and new approaches to electronic transport and device modeling have become necessary. Examples are the introduction of vertical MOSFETs in addition to the planar ones to enable the multi-gate approach as well as the development of new tunneling, high-electron mobility, and single-electron devices. The search for new materials such as nanowires, nanotubes, and 2D materials for the transistor channel, dielectrics, and interconnects has been part of the process. New electronic devices, often consisting of nanoscale heterojunctions, have been developed for light emission, transmission, and detection in optoelectronic and photonic systems, as well for new chemical, biological, and environmental sensors. This Special Issue focuses on the design, fabrication, modeling, and demonstration of nanodevices for electronic, optoelectronic, and sensing applications
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