Current and Voltage Mode Multiphase Sinusoidal Oscillators Using CBTAs

Current-mode (CM) and voltage-mode (VM) multiphase sinusoidal oscillator (MSO) structures using current backward transconductance amplifier (CBTA) are proposed. The proposed oscillators can generate n current or voltage signals (n being even or odd) equally spaced in phase. n+1 CBTAs, n grounded capacitors and a grounded resistor are used for nth-state oscillator. The oscillation frequency can be independently controlled through transconductance (gm) of the CBTAs which are adjustable via their bias currents. The effects caused by the non-ideality of the CBTA on the oscillation frequency and condition have been analyzed. The performance of the proposed circuits is demonstrated on third-stage and fifth-stage MSOs by using PSPICE simulations based on the 0.25 µm TSMC level-7 CMOS technology parameters

Arbitrarily Tunable Phase Shift in Low-Frequency Multiphase Oscillator

A special electronically tunable multiphase oscillator with arbitrarily and continuously adjustable phase shifts is introduced. Our design assumes to set the phase around the asymptotical limit of 180.. These features cannot be easily achieved in a standard way, i.e., any simple single-phase oscillator supplemented by a first-order adjustable all-pass (AP) section (shifter). The proposed design uses an electronically linearly tunable quadrature oscillator with a frequency range from 0.98 up to 12.54 kHz. It also offers multiples of 45. as the initial setting of the phase shift tuning region. The example of operation shows the adjustment of the phase shift at a specific frequency (10 kHz) within the range of +/- 45 degrees. and around -180 degrees, -135 degrees, and -90 degrees. This variability is not available in standard cases without the use of several AP sections. The current value of the phase shift of the presented oscillator is electronically controlled and does not influence the oscillation frequency and condition of oscillation. Output levels of produced signals are not influenced by this tuning process and are in the range of several hundreds of mV. Two applications of the oscillator are proposed. The first one focuses on low-bitrate modulation systems [phase shift keying (PSK)] while in the second one, our circuit represents a source of phase-adjustable signals in acoustic experiments. Discrete passive elements and active devices (special multipliers having current output terminals, unity-gain differential voltage buffers) fabricated in 0.35 mu m I3T25 ON Semiconductor 3.3 V CMOS process are used in experimental verification

Fractionally-addressed delay lines

While traditional implementations of variable-length digital delay lines are based on a circular buffer accessed by two pointers, we propose an implementation where a single fractional pointer is used both for read and write operations. On modern general-purpose architectures, the proposed method is nearly as efficient as the popularinterpolated circular buffer, and it behaves well for delay-length modulations commonly found in digital audio effects. The physical interpretation of the new implementation shows that it is suitable for simulating tension or density modulations in wave-propagating media.Comment: 11 pages, 19 figures, to be published in IEEE Transactions on Speech and Audio Processing Corrected ACM-clas

A Novel Pseudo-Differential Integer/Fractional-Order Voltage-Mode All-Pass Filter

The paper presents the first- (integer) and fractional-order case studies of a novel pseudo-differential (P-D) voltage-mode all-pass filter (APF) employing a single differential voltage current conveyor (DVCC), one resistor, and a single grounded capacitor. The proposed filter brings significant reduction of complexity in comparison to available fully-differential or P-D filter topologies. Moreover, it was also shown that fractional-order capacitor can be used for gain response compensation of the proposed APF. The theoretical results of 0.8th and 1st-order APF were verified by Cadence IC6 Spectre simulations using new structure of DVCC via TSMC 0.18 µm CMOS process parameters supplied with ±0.9 V voltages

Voltage Gain-Controlled Third-Generation Current Conveyor and its All-Pass Filter Verification

The paper presents a new active building block (ABB) called minus-type voltage gain-controlled third-generation current conveyor (VGC-CCIII) in which the voltage gain between Y to X terminal can be controlled. The usefulness of the tunable feature in the presented ABB is demonstrated in current-mode {0.3rd; 0.5th; 0.7th; 1st}-order all-pass filter (APF) employing single VGC-CCIII, one capacitor, and one resistor. The theoretical results of the integer- and fractional-order APF are verified by SPICE simulations based on readily available IC OPA860 macromodel, which can also be used in experiments

Analog Implementation of Fractional-Order Elements and Their Applications

With advancements in the theory of fractional calculus and also with widespread engineering application of fractional-order systems, analog implementation of fractional-order integrators and differentiators have received considerable attention. This is due to the fact that this powerful mathematical tool allows us to describe and model a real-world phenomenon more accurately than via classical “integer” methods. Moreover, their additional degree of freedom allows researchers to design accurate and more robust systems that would be impractical or impossible to implement with conventional capacitors. Throughout this thesis, a wide range of problems associated with analog circuit design of fractional-order systems are covered: passive component optimization of resistive-capacitive and resistive-inductive type fractional-order elements, realization of active fractional-order capacitors (FOCs), analog implementation of fractional-order integrators, robust fractional-order proportional-integral control design, investigation of different materials for FOC fabrication having ultra-wide frequency band, low phase error, possible low- and high-frequency realization of fractional-order oscillators in analog domain, mathematical and experimental study of solid-state FOCs in series-, parallel- and interconnected circuit networks. Consequently, the proposed approaches in this thesis are important considerations in beyond the future studies of fractional dynamic systems

Analogue filter networks: developments in theory, design and analyses

Not availabl

Analogue emulators of fractional-order circuits

Diplomová práce se zabývá problematikou obvodů neceločíselných řádů. V první části je pojednáno o této problematice, dále byly uvedeny jednotlivé metody návrhů a typy obvodů, které lze v praxi využít. Následující kapitola popisuje použité aktivní prvky v této diplomové práci. V následující kapitole byl uveden praktický postup návrhu konvertorů impedance a následná implementace prvků s neceločíselným řádem do obvodů. Tyto struktury s neceločíselným řádem byly implementovány do kmitočtového filtru s neceločíselným řádem. V praktické části také byly provedeny parazitní analýza a stabilita kmitočtového filtru s fraktálním řádem.Diploma thesis deals with circuits contain fractional-order elements. The first part of this paper deals with this problem, there were also described methods of design fractionalorder elements and types of circuits containing the fractiona-order elements which can be applied in practice. Used active elements for practical part can be found in the second chapter. Design of GIC circuits and implementation of fractional-order element inside the circuit are shown in the last chapture. Parasitic analysis and stability of frequency filter containing fractional-order element had been also described.

High performance RF and baseband building blocks for wireless receivers

Because of the unique architecture of wireless receivers, a designer must understand both the high frequency aspects as well as the low-frequency analog considerations for different building blocks of the receiver. The primary goal of this research work is to explore techniques for implementing high performance RF and baseband building blocks for wireless applications. Several novel techniques to improve the performance of analog building blocks are presented. An enhanced technique to couple two LC resonators is presented which does not degrade the loaded quality factor of the resonators which results in an increased dynamic range. A novel technique to automatically tune the quality factor of LC resonators is presented. The proposed scheme is stable and fast and allows programming both the quality factor and amplitude response of the LC filter. To keep the oscillation amplitude of LC VCOs constant and thus achieving a minimum phase noise and a reliable startup, a stable amplitude control loop is presented. The proposed scheme has been also used in a master-slave quality factor tuning of LC filters. An efficient and low-cost architecture for a 3.1GHz-10.6GHz ultra-wide band frequency synthesizer is presented. The proposed scheme is capable of generating 14A novel pseudo-differential transconductance amplifier is presented. The proposed scheme takes advantage of the second-order harmonic available at the output current of pseudo-differential structure to cancel the third-order harmonic distortion. A novel nonlinear function is proposed which inherently removes the third and the fifth order harmonics at its output signal. The proposed nonlinear block is used in a bandpass-based oscillator to generate a highly linear sinusoidal output. Finally, a linearized BiCMOS transconductance amplifier is presented. This transconductance is used to build a third-order linear phase low pass filter with a cut-off frequency of 264MHz for an ultra-wide band receiver. carrier frequencies