kk-block parallel addition versus 11-block parallel addition in non-standard numeration systems

Parallel addition in integer base is used for speeding up multiplication and division algorithms. $k$-block parallel addition has been introduced by Kornerup in 1999: instead of manipulating single digits, one works with blocks of fixed length $k$. The aim of this paper is to investigate how such notion influences the relationship between the base and the cardinality of the alphabet allowing parallel addition. In this paper, we mainly focus on a certain class of real bases --- the so-called Parry numbers. We give lower bounds on the cardinality of alphabets of non-negative integer digits allowing block parallel addition. By considering quadratic Pisot bases, we are able to show that these bounds cannot be improved in general and we give explicit parallel algorithms for addition in these cases. We also consider the $d$-bonacci base, which satisfies the equation $X^d = X^{d-1} + X^{d-2} + \cdots + X + 1$. If in a base being a $d$-bonacci number $1$-block parallel addition is possible on the alphabet $\mathcal{A}$, then $\#\mathcal{A} \geq d+1$; on the other hand, there exists a $k\in\mathbb{N}$ such that $k$-block parallel addition in this base is possible on the alphabet $\{0,1,2\}$, which cannot be reduced. In particular, addition in the Tribonacci base is $14$-block parallel on alphabet $\{0,1,2\}$.Comment: 21 page

Theoretical Informatics and Applications Will be set by the publisher Informatique Théorique et Applications MINIMAL DIGIT SETS FOR PARALLEL ADDITION IN NON-STANDARD NUMERATION SYSTEMS

Abstract. We study parallel algorithms for addition of numbers having finite representation in a positional numeration system defined by a base β in C and a finite digit set A of contiguous integers containing 0. For a fixed base β, we focus on the question of the size of the alphabet allowing to perform addition in constant time independently of the length of representation of the summands. We produce lower bounds on the size of such alphabet A. For several types of well studied bases (negative integer, complex numbers −1 + ı, 2ı, and ı √ 2, quadratic Pisot unit, and the non-integer rational base), we give explicit parallel algorithms performing addition in constant time. Moreover we show that digit sets used by these algorithms are the smallest possible

HIGH-SPEED CO-PROCESSORS BASED ON REDUNDANT NUMBER SYSTEMS

There is a growing demand for high-speed arithmetic co-processors for use in applications with computationally intensive tasks. For instance, Fast Fourier Transform (FFT) co-processors are used in real-time multimedia services and financial applications use decimal co-processors to perform large amounts of decimal computations. Using redundant number systems to eliminate word-wide carry propagation within interim operations is a well-known technique to increase the speed of arithmetic hardware units. Redundant number systems are mostly useful in applications where many consecutive arithmetic operations are performed prior to the final result, making it advantageous for arithmetic co-processors. This thesis discusses the implementation of two popular arithmetic co-processors based on redundant number systems: namely, the binary FFT co-processor and the decimal arithmetic co-processor. FFT co-processors consist of several consecutive multipliers and adders over complex numbers. FFT architectures are implemented based on fixed-point and floating-point arithmetic. The main advantage of floating-point over fixed-point arithmetic is the wide dynamic range it introduces. Moreover, it avoids numerical issues such as scaling and overflow/underflow concerns at the expense of higher cost. Furthermore, floating-point implementation allows for an FFT co-processor to collaborate with general purpose processors. This offloads computationally intensive tasks from the primary processor. The first part of this thesis, which is devoted to FFT co-processors, proposes a new FFT architecture that uses a new Binary-Signed Digit (BSD) carry-limited adder, a new floating-point BSD multiplier and a new floating-point BSD three-operand adder. Finally, a new unit labeled as Fused-Dot-Product-Add (FDPA) is designed to compute AB+CD+E over floating-point BSD operands. The second part of the thesis discusses decimal arithmetic operations implemented in hardware using redundant number systems. These operations are popularly used in decimal floating-point co-processors. A new signed-digit decimal adder is proposed along with a sequential decimal multiplier that uses redundant number systems to increase the operational frequency of the multiplier. New redundant decimal division and square-root units are also proposed. The architectures proposed in this thesis were all implemented using Hardware-Description-Language (Verilog) and synthesized using Synopsys Design Compiler. The evaluation results prove the speed improvement of the new arithmetic units over previous pertinent works. Consequently, the FFT and decimal co-processors designed in this thesis work with at least 10% higher speed than that of previous works. These architectures are meant to fulfill the demand for the high-speed co-processors required in various applications such as multimedia services and financial computations

Cutting Edge Nanotechnology

The main purpose of this book is to describe important issues in various types of devices ranging from conventional transistors (opening chapters of the book) to molecular electronic devices whose fabrication and operation is discussed in the last few chapters of the book. As such, this book can serve as a guide for identifications of important areas of research in micro, nano and molecular electronics. We deeply acknowledge valuable contributions that each of the authors made in writing these excellent chapters