On applying the set covering model to reseeding

The Functional BIST approach is a rather new BIST technique based on exploiting embedded system functionality to generate deterministic test patterns during BIST. The approach takes advantages of two well-known testing techniques, the arithmetic BIST approach and the reseeding method. The main contribution of the present paper consists in formulating the problem of an optimal reseeding computation as an instance of the set covering problem. The proposed approach guarantees high flexibility, is applicable to different functional modules, and, in general, provides a more efficient test set encoding then previous techniques. In addition, the approach shorts the computation time and allows to better exploiting the tradeoff between area overhead and global test length as well as to deal with larger circuits

Combinatorial Design and Analysis of Optimal Multiple Bus Systems for Parallel Algorithms.

This dissertation develops a formal and systematic methodology for designing optimal, synchronous multiple bus systems (MBSs) realizing given (classes of) parallel algorithms. Our approach utilizes graph and group theoretic concepts to develop the necessary model and procedural tools. By partitioning the vertex set of the graphical representation CFG of the algorithm, we extract a set of interconnection functions that represents the interprocessor communication requirement of the algorithm. We prove that the optimal partitioning problem is NP-Hard. However, we show how to obtain polynomial time solutions by exploiting certain regularities present in many well-behaved parallel algorithms. The extracted set of interconnection functions is represented by an edge colored, directed graph called interconnection function graph (IFG). We show that the problem of constructing an optimal MBS to realize an IFG is NP-Hard. We show important special cases where polynomial time solutions exist. In particular, we prove that polynomial time solutions exist when the IFG is vertex symmetric. This is the case of interest for the vast majority of important interconnection function sets, whether extracted from algorithms or correspond to existing interconnection networks. We show that an IFG is vertex symmetric if and only if it is the Cayley color graph of a finite group $\Gamma$ and its generating set $\Delta.$ Using this property, we present a particular scheme to construct a symmetric $MBS\ M(\Gamma,\Delta)$ with minimum number of buses as well as minimum number of interfaces realizing a vertex symmetric IFG. We demonstrate several advantages of the optimal $MBS\ M(\Gamma,\Delta)$ in terms of its symmetry, number of ports per processor, number of neighbors per processor, and the diameter. We also investigate the fault tolerant capabilities and performance degradation of $M(\Gamma,\Delta)$ in the case of a single bus failure, single driver failure, single receiver failure, and single processor failure. Further, we address the problem of designing an optimal MBS realizing a class of algorithms when the number of buses and/or processors in the target MBS are specified. The optimality criteria are maximizing the speed and minimizing the number of interfaces

Intelligent approaches to VLSI routing

Very Large Scale Integrated-circuit (VLSI) routing involves many large-size and complex problems and most of them have been shown to be NP-hard or NP-complete. As a result, conventional approaches, which have been successfully used to handle relatively small-size routing problems, are not suitable to be used in tackling large-size routing problems because they lead to \u27combinatorial explosion\u27 in search space. Hence, there is a need for exploring more efficient routing approaches to be incorporated into today\u27s VLSI routing system. This thesis strives to use intelligent approaches, including symbolic intelligence and computational intelligence, to solve three VLSI routing problems: Three-Dimensional (3-D) Shortest Path Connection, Switchbox Routing and Constrained Via Minimization. The 3-D shortest path connection is a fundamental problem in VLSI routing. It aims to connect two terminals of a net that are distributed in a 3-D routing space subject to technological constraints and performance requirements. Aiming at increasing computation speed and decreasing storage space requirements, we present a new A* algorithm for the 3-D shortest path connection problem in this thesis. This new A*algorithm uses an economical representation and adopts a novel back- trace technique. It is shown that this algorithm can guarantee to find a path if one exists and the path found is the shortest one. In addition, its computation speed is fast, especially when routed nets are spare. The computational complexities of this A* algorithm at the best case and the worst case are O(Ɩ) and 0(Ɩ3), respectively, where Ɩ is the shortest path length between the two terminals. Most importantly, this A\u27 algorithm is superior to other shortest path connection algorithms as it is economical in terms of storage space requirement, i.e., 1 bit/grid. The switchbox routing problem aims to connect terminals at regular intervals on the four sides of a rectangle routing region. From a computational point of view, the problem is NP-hard. Furthermore, it is extremely complicated and as the consequence no existing algorithm can guarantee to find a solution even if one exists no matter how high the complexity of the algorithm is. Previous approaches to the switch box routing problem can be divided into algorithmic approaches and knowledge-based approaches. The algorithmic approaches are efficient in computational time, but they are unsucessful at achieving high routing completion rate, especially for some dense and complicated switchbox routing problems. On the other hand, the knowledge-based approaches can achieve high routing completion rate, but they are not efficient in computation speed. In this thesis we present a hybrid approach to the switchbox routing problem. This hybrid approach is based on a new knowledge-based routing technique, namely synchronized routing, and combines some efficient algorithmic routing techniques. Experimental results show it can achieve the high routing completion rate of the knowledge-based approaches and the high efficiency of the algorithmic approaches. The constrained via minimization is an important optimization problem in VLSI routing. Its objective is to minimize the number of vias introduced in VLSI routing. From computational perspective, the constrained via minimization is NP-complete. Although for a special case where the number of wire segments splits at a via candidate is not more than three, elegant theoretical results have been obtained. For a general case in which there exist more than three wire segment splits at a via candidate few approaches have been proposed, and those approaches are only suitable for tackling some particular routing styles and are difficult or impossible to adjust to meet practical requirements. In this thesis we propose a new graph-theoretic model, namely switching graph model, for the constrained via minimization problem. The switching graph model can represent both grid-based and grid less routing problems, and allows arbitrary wire segments split at a via candidate. Then on the basis of the model, we present the first genetic algorithm for the constrained via minimization problem. This genetic algorithm can tackle various kinds of routing styles and be configured to meet practical constraints. Experimental results show that the genetic algorithm can find the optimal solutions for most cases in reasonable time

Modernizing payment systems in emerging economies

The authors address the following questions in this overview of payment systems: What is a payment system? How can efficient systems contribute to the development of modern, market-based financial institutions and markets? What elements are necessary for payment systems to operate efficiently? What are the operational characteristics of a modern payment system? What is the World Bank approach to selected payment system initiatives, design, and development? Effective, efficient payment systems, they conclude, are vital for the economic development of emerging economies. Efficient payment systems help promote the development of commerce, enhance economic policy oversight, control the risk inherent in moving large values, and reduce the financial, capital and human resources devoted to the transfer of payments. Many emerging economies lack the financial and technical resources to develop such systems. Many turn technical resources to develop such systems. Many turn to the World Bank and other international agencies for assistance. Unfortunately, some believe that the entire solution for an effective payment system rests in obtaining modern computer hardware and believe the World Bank's sole contribution is to finance hardware costs. Hardware procurement alone will not solve problems of payment systems. These countries need organizational plans and structure for national payment systems before they spend money on computer equipment. They often lack the expertise to design and operate modern payment systems, so they may need technical assistance from financial experts before they invest in systems development. The design of a new payment system should be kept simple. Many emerging economies lack the infrastructure and banking sophistication to leapfrog from basic to state-of-the-art payment systems. The first task is to fix the most serious problems. The second is to upgrade the current systems incrementally, to meet basic standards of timeliness, security, and reliability. As these improvements are made, the countries can turn their attention to long-term, advanced solutions. Each country's payments system is unique. To simply import another country's system without adjusting for the target country's geography, infrastructure, banking and legal structures, culture, and needs could lead to suboptimal solutions. Development of the system should follow a disciplined plan for defining the needs of users and for organizing the project team and project goals.Payment Systems&Infrastructure,Banks&Banking Reform,Economic Theory&Research,Financial Intermediation,Information Technology

A fault-tolerant multiprocessor architecture for aircraft, volume 1

A fault-tolerant multiprocessor architecture is reported. This architecture, together with a comprehensive information system architecture, has important potential for future aircraft applications. A preliminary definition and assessment of a suitable multiprocessor architecture for such applications is developed

Innovative primary frequency control in low-inertia power systems based on wide-area RoCoF sharing

Future plans for integration of large nonsynchronous generation and the expansion of the power system in the Nordic countries are a concern to transmission system operators (TSOs) due to the common interconnections and electricity exchanges among these operative areas. The expected reduction in the inertia anticipates an alteration of the frequency response, provoking high Rate of Change of Frequency (RoCoF) slopes that can jeopardize the security of the interconnected systems. Since power generation in the Nordic countries such as Sweden, Finland and Norway is hydro-dominated, in this paper, we propose a novel solution to tackle this problem including Wide Area Measurements (WAMS) to monitor and share the RoCoF in remote areas with lower inertia to enhance their primary frequency control. To demonstrate the effectiveness of the proposed solution, first a test benchmark control with optimized parameters is developed and later compared against the proposed method. Additionally, since the proposed solution is based on measurements from remote locations in order to guarantee stability of the system the impact of delays in the communication channels is also included in the problem formulation

Multiprocessing techniques for unmanned multifunctional satellites Final report,

Simulation of on-board multiprocessor for long lived unmanned space satellite contro

Concepts for design of an energy management system incorporating dispersed storage and generation

New forms of generation based on renewable resources must be managed as part of existing power systems in order to be utilized with maximum effectiveness. Many of these generators are by their very nature dispersed or small, so that they will be connected to the distribution part of the power system. This situation poses new questions of control and protection, and the intermittent nature of some of the energy sources poses problems of scheduling and dispatch. Under the assumption that the general objectives of energy management will remain unchanged, the impact of dispersed storage and generation on some of the specific functions of power system control and its hardware are discussed