Successive-approximation-register based quantizer design for high-speed delta-sigma modulators

High-speed delta-sigma modulators are in high demand for applications such as wire-line and wireless communications, medical imaging, RF receivers and high-definition video processing. A high-speed delta-sigma modulator requires that all components of the delta-sigma loop operate at the desired high frequency. For this reason, it is essential that the quantizer used in the delta-sigma loop operate at a high sampling frequency. This thesis focuses on the design of high-speed time-interleaved multi-bit successive-approximation-register (SAR) quantizers. Design techniques for high-speed medium-resolution SAR analog-to-digital converters (ADCs) using synchronous SAR logic are proposed. Four-bit and 8-bit 5 GS/s SAR ADCs have been implemented in 65 nm CMOS using 8-channel and 16-channel time-interleaving respectively. The 4-bit SAR ADC achieves SNR of 24.3 dB, figure-of-merit (FoM) of 638 fJ/conversion-step and 42.6 mW power consumption, while the 8-bit SAR ADC achieves SNR of 41.5 dB, FoM of 191 fJ/conversion-step and 92.8 mW power consumption. High-speed operation is achieved by optimizing the critical path in the SAR ADC loop. A sampling network with a split-array with unit bridge capacitor topology is used to reduce the area of the sampling network and switch drivers

Síntese Digital Direta

Os projetos tradicionais de sintetizadores de frequência de elevada largura de banda utilizam um circuito fechado de fase (PLL). Um sintetizador digital direto, ou na terminologia inglesa, Direct Digital Dynthesis (DDS) oferece muitas vantagens significativas sobre as abordagens PLL como, por exemplo, um tempo de estabilização rápido, resolução de frequência sub-Hertz, resposta de comutação de fase contínua e baixo ruído de fase. Embora o princípio do DDS seja conhecido há muitos anos, o DDS não desempenhou um papel dominante na geração de frequência de banda larga até recentemente. Os DDSs iniciais eram limitados a produzir frequências estreitamente espaçadas com pequena largura de banda, devido a limitações da lógica digital e das tecnologias de conversão D/A. As vantagens recentes nas tecnologias de circuitos integrados (CI) trouxeram um progresso notável nesta área. Ao programar um DDS, é possível adaptar as larguras de banda de canal, formatos de modulação, salto de frequência e taxas de dados. Este é um passo importante em direção a um “software-rádio” que pode ser usado em vários sistemas. Um DDS pode ser aplicado no modulador ou demodulador nos sistemas de comunicação. O objetivo desta pesquisa foi encontrar um frontend ideal para um transmissor, concentrando-se nas implementações de circuito do DDS, mas a pesquisa também inclui a interface para circuitos de banda base e aspetos de design de nível de sistema de sistemas de comunicação digital.Traditional high-bandwidth frequency synthesizer designs utilize a phase closed loop (PLL). A direct digital synthesizer, or in English terminology, Direct Digital Dynthesis (DDS) offers many significant advantages over PLL approaches such as a fast-settling time, sub-Hertz frequency resolution, continuous phase switching response and low phase noise. Although the principle of DDS has been known for many years, DDS has not played a dominant role in broadband frequency generation until recently. Early DDSs were limited to producing closely spaced frequencies with low bandwidth, due to limitations of digital logic and D/A conversion technologies. Recent advances in integrated circuit (IC) technologies have brought remarkable progress in this area. When programming a DDS, it is possible to adapt channel bandwidths, modulation formats, frequency hopping and data rates. This is an important step towards “radio software” that can be used on multiple systems. A DDS can be applied in the modulator or demodulator in the communication systems. The purpose of this research was to find an ideal frontend for a transmitter, focusing on the circuit implementations of DDS, but the research also includes the interface to baseband circuits and system-level design aspects of digital communication systems