4 research outputs found
Optimization of DSSS Receivers Using Hardware-in-the-Loop Simulations
Over the years, there has been significant interest in defining a hardware abstraction layer to facilitate code reuse in software defined radio (SDR) applications. Designers are looking for a way to enable application software to specify a waveform, configure the platform, and control digital signal processing (DSP) functions in a hardware platform in a way that insulates it from the details of realization.
This thesis presents a tool-based methodolgy for developing and optimizing a Direct Sequence Spread Spectrum (DSSS) transceiver deployed in custom hardware like Field Programmble Gate Arrays (FPGAs). The system model consists of a tranmitter which employs a quadrature phase shift keying (QPSK) modulation scheme, an additive white Gaussian noise (AWGN) channel, and a receiver whose main parts consist of an analog-to-digital converter (ADC), digital down converter (DDC), image rejection low-pass filter (LPF), carrier phase locked loop (PLL), tracking locked loop, down-sampler, spread spectrum correlators, and rectangular-to-polar converter.
The design methodology is based on a new programming model for FPGAs developed in the industry by Xilinx Inc. The Xilinx System Generator for DSP software tool provides design portability and streamlines system development by enabling engineers to create and validate a system model in Xilinx FPGAs. By providing hierarchical modeling and automatic HDL code generation for programmable devices, designs can be easily verified through hardware-in-the-loop (HIL) simulations.
HIL provides a significant increase in simulation speed which allows optimization of the receiver design with respect to the datapath size for different functional parts of the receiver. The parameterized datapath points used in the simulation are ADC resolution, DDC datapath size, LPF datapath size, correlator height, correlator datapath size, and rectangular-to-polar datapath size. These parameters are changed in the software enviornment and tested for bit error rate (BER) performance through real-time hardware simualtions. The final result presents a system design with minimum harware area occupancy relative to an acceptable BER degradation
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Study of continuous-phase four-state modulation for cordless telecommunications. Assessment by simulation of CP-QFSK as an alternative modulation scheme for TDMA digital cordless telecommunications systems operating in indoor applications
One of the major driving elements behind the explosive boom in wireless revolution is the advances in the field of modulation which plays a fundamental role in any communication system, and especially in cellular radio systems. Hence, the elaborate choice of an efficient modulation scheme is of paramount importance in the design and employment of any communications system. Work presented in this thesis is an investigation (study) of the feasibility of whether multilevel FSK modulation scheme would provide a viable alternative modem that can be employed in TDMA cordless communications systems. In the thesis the design and performance analysis of a non-coherent multi-level modem that offers a great deal of bandwidth efficiency and hardware simplicity is studied in detail. Simulation results demonstrate that 2RC pre-modulation filter pulse shaping with a modulation index of 0.3, and pre-detection filter normalized equivalent noise bandwidth of 1.5 are optimum system parameter values. Results reported in chapter 5 signify that an adjacent channel rejection factor of around 40 dB has been achieved at channel spacing of 1.5 times the symbol rate while the DECT system standards stipulated a much lower rejection limit criterion (25-30dB), implying that CP-QFSK modulation out-performs the conventional GMSK as it causes significantly less ACI, thus it is more spectrally efficient in a multi-channel system. However, measured system performance in terms of BER indicates that this system does not coexist well with other interferers as at delay spreads between 100ns to 200ns, which are commonly encountered in such indoor environment, a severe degradation in system performance apparently caused by multi-path fading has been noticed, and there exists a noise floor of about 40 dB, i.e. high irreducible error rate of less than 5.10-3. Implementing MRC diversity combiner and BCH codec has brought in a good gain.Higher Education Ministr
NASA Tech Briefs, August 2000
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