Image enhancement and segmentation on simultaneous latent fingerprint detection

A simultaneous latent fingerprint (SLF) image consists of multi-print of individual fingerprints that is lifted from a surface, typically at the crime scenes. Due to the nature and the poor quality of latent fingerprint image, segmentation becomes an important and very challenging task. This thesis presents an algorithm to segment individual fingerprints for SLF image. The algorithm aim to separate the fingerprint region of interest from image background, which identifies the distal phalanx portion of each finger that appears in SLF image. The algorithm utilizes ridge orientation and frequency features based on block-wise pixels. A combination of Gabor Filter and Fourier transform is implemented in the normalization stage. In the pre-processing stage, a modified version of Histogram equalization is proposed known as Alteration Histogram Equalization (AltHE). Sliding windows are applied to create bounding boxes in order to find out the distal phalanges region at the segmentation stage. To verify the capability of the proposed segmentation algorithm, the segmentation results is evaluated in two aspects: a comparison with the ground truth foreground and matching performance based on segmented region. The ground truth foreground refers to the manual mark up region of interest area. In order to evaluate the performance of this method, experiments are performed on the Indian Institute of Information Technology Database- Simultaneous Latent Fingerprint (IIITD-SLF). Using the proposed algorithm, the segmented images were supplied as the input image for the matching process via a state art of matcher, VeriFinger SDK. Segmentation of 240 images is performed and compared with manual segmentation methods. The results show that the proposed algorithm achieves a correct segmentation of 77.5% of the SLF images under test

Implementation of the Enhanced Fingerprint Authentication in the ATM System Using ATmega128 with GSM Feedback Mechanism

ATM was introduced to boost the cashless policy in Nigeria. Current trend of Cybercrime facilitate the need for an enhanced fingerprint application on ATM machine with GSM Feedback mechanism. The mechanism enable unassigned fingerprint authentication of customers with quick code and secret code. The project enhances the security authentication of customers using ATM. A core controller using fingerprint recognition system of ATmega128 in-system programmable flash is explored. An SM630 fingerprint module is used to capture fingerprints with DSP processor and optical sensor for verification, using AT command of GSM module for feedback text messaging (i.e. sending of Quick and Secret-Codes respectively). Upon system testing of capable reduction of ATM fraud using C program, the new method of authentication is presented

Enhanced convnet based Latent Finger Print Recognition

Latent finger print recognition plays an important role in forensic, criminal cases etc. The latent images will not be recognised easily since they are impartial images, which find difficult to match with the registered database. Due to noisy images, it is very difficult for recognition. Autoencoder plays an important role in pre-processing the latent image. ConvNetbased method is an efficient approach used for latent image recognition. For each minutiae extraction, ConvNet descriptor is performed. Both minutiae and texture matcher is considered for comparison. This technique is compared with existing methods which shows, that the proposed method provides a higher accuracy than the existing methods like CNN, skeleton approach nonlinear mapping and product quantization. The proposed method provides an accuracy of 76.4%, 80.4% and 86.4% for rank1,5 and 10 respectively

A Review of Fingerprint Feature Representations and Their Applications for Latent Fingerprint Identification: Trends and Evaluation

Latent fingerprint identification is attracting increasing interest because of its important role in law enforcement. Although the use of various fingerprint features might be required for successful latent fingerprint identification, methods based on minutiae are often readily applicable and commonly outperform other methods. However, as many fingerprint feature representations exist, we sought to determine if the selection of feature representation has an impact on the performance of automated fingerprint identification systems. In this paper, we review the most prominent fingerprint feature representations reported in the literature, identify trends in fingerprint feature representation, and observe that representations designed for verification are commonly used in latent fingerprint identification. We aim to evaluate the performance of the most popular fingerprint feature representations over a common latent fingerprint database. Therefore, we introduce and apply a protocol that evaluates minutia descriptors for latent fingerprint identification in terms of the identification rate plotted in the cumulative match characteristic (CMC) curve. From our experiments, we found that all the evaluated minutia descriptors obtained identification rates lower than 10% for Rank-1 and 24% for Rank-100 comparing the minutiae in the database NIST SD27, illustrating the need of new minutia descriptors for latent fingerprint identification.This work was supported in part by the National Council of Science and Technology of Mexico (CONACYT) under Grant PN-720 and Grant 63894

The State of Utah Plaintiff/Appellee v. Raymond Michael Quintana Defendant/Appellant. : Brief of Appellant

IN THE UTAH COURT OF APPEALS THE STATE OF UTAH, : Plaintiff/Appellee, : v. : RAYMOND MICHAEL QUINTANA, : Case No. 20030471-CA Defendant/Appellant. : BRIEF OF APPELLANT Appeal from convictions for: (1) burglary, a second degree felony in violation of Utah Code Annotated section 76-6-202 (Supp. 2003); and, (2) theft, a class B misdemeanor in violation of Utah Code Annotated section 76-6-404 (1999), in the Third Judicial District Court, in and for Salt Lake County, State of Utah, the Honorable Robin W. Reese, presiding

Accelerating Pattern Recognition Algorithms On Parallel Computing Architectures

The move to more parallel computing architectures places more responsibility on the programmer to achieve greater performance. The programmer must now have a greater understanding of the underlying architecture and the inherent algorithmic parallelism. Using parallel computing architectures for exploiting algorithmic parallelism can be a complex task. This dissertation demonstrates various techniques for using parallel computing architectures to exploit algorithmic parallelism. Specifically, three pattern recognition (PR) approaches are examined for acceleration across multiple parallel computing architectures, namely field programmable gate arrays (FPGAs) and general purpose graphical processing units (GPGPUs). Phase-only filter correlation for fingerprint identification was studied as the first PR approach. This approach\u27s sensitivity to angular rotations, scaling, and missing data was surveyed. Additionally, a novel FPGA implementation of this algorithm was created using fixed point computations, deep pipelining, and four computation phases. Communication and computation were overlapped to efficiently process large fingerprint galleries. The FPGA implementation showed approximately a 47 times speedup over a central processing unit (CPU) implementation with negligible impact on precision. For the second PR approach, a spiking neural network (SNN) algorithm for a character recognition application was examined. A novel FPGA implementation of the approach was developed incorporating a scalable modular SNN processing element (PE) to efficiently perform neural computations. The modular SNN PE incorporated streaming memory, fixed point computation, and deep pipelining. This design showed speedups of approximately 3.3 and 8.5 times over CPU implementations for 624 and 9,264 sized neural networks, respectively. Results indicate that the PE design could scale to process larger sized networks easily. Finally for the third PR approach, cellular simultaneous recurrent networks (CSRNs) were investigated for GPGPU acceleration. Particularly, the applications of maze traversal and face recognition were studied. Novel GPGPU implementations were developed employing varying quantities of task-level, data-level, and instruction-level parallelism to achieve efficient runtime performance. Furthermore, the performance of the face recognition application was examined across a heterogeneous cluster of multi-core and GPGPU architectures. A combination of multi-core processors and GPGPUs achieved roughly a 996 times speedup over a single-core CPU implementation. From examining these PR approaches for acceleration, this dissertation presents useful techniques and insight applicable to other algorithms to improve performance when designing a parallel implementation