5 research outputs found

    A Fast and Accurate Process Variation-Aware Modeling Technique for Resistive Bridge Defects

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    On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing

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    Resistive defects are gaining importance in very-deepsubmicron technologies, but their detection conditions are not trivial. Test application can be performed under reduced temperature and/or voltage in order to improve detection of these defects. This is the first analytical study of resistive bridge defect coverage of CMOS ICs under low-temperature and mixed low-temperature, low-voltage conditions. We extend a resistive bridging fault model in order to account for temperature-induced changes in detection conditions. We account for changes in both the parameters of transistors involved in the bridge and the resistance of the short defect itself. Using a resistive bridging fault simulator, we determine fault coverage for low-temperature testing and compare it to the numbers obtained at nominal conditions. We also quantify the coverage of flaws, i.e. defects that are redundant at nominal conditions but could deteriorate and become earlylife failures. Finally, we compare our results to the case of low-voltage testing and comment on combination of these two techniques. Keywords: Temperature testing, Low-voltage testing, Resistive defects, Early-life failure

    Thermal Issues in Testing of Advanced Systems on Chip

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