Timing-Constrained Global Routing with RC-Aware Steiner Trees and Routing Based Optimization

In this thesis we consider the global routing problem, which arises as one of the major subproblems in the physical design step in VLSI design. In global routing, we are given a three-dimensional grid graph G with edge capacities representing available routing space, and we have to connect a set of nets in G without overusing any edge capacities. Here, each net consists of a set of pins corresponding to vertices of G, where one pin is the sender of signals, while all other pins are receivers. Traditionally, next to obeying all edge capacity constraints, the objective has been to minimize wire length and possibly via (edges in z-direction) count, and timing constraints on the chip were only modeled indirectly. We present a new approach, where timing constraints are modeled directly during global routing: In joint work with Stephan Held, Dirk Mueller, Daniel Rotter, Vera Traub and Jens Vygen, we extend the modeling of global routing as a Min-Max Resource Sharing Problem to also incorporate timing constraints. For measuring signal delays we use the well-established Elmore delay model. One of the key subproblems here is the computation of Steiner trees minimizing a weighted sum of routing space usages and signal delays. For k pins, this problem is NP-hard to approximate within o(log k), and even the special case k = 2 is NP-hard, as was shown by Haehnle and Rotter. We present a fast approximation algorithm with strong approximation bounds for the case k = 2. For k > 2 we use a multi-stage approach based on modifying the topology of a short Steiner tree and using our algorithm for the two-pin case for computing new connections. Moreover, we present a layer assignment algorithm that assigns z-coordinates to the edges of a given two-dimensional tree. We also discuss the topic of routing based optimization. Here, the starting point is a complete routing, and timing optimization tools make changes that require incremental adaptations of the underlying routing. We investigate several aspects of this problem and derive a new routing flow that includes our timing-aware global router and routing based optimization steps. We evaluate our results from this thesis in practice on industrial 14nm microprocessor designs from IBM. Our theoretical results are validated in practice by a strong performance of our timing-aware global routing framework and our new routing flow, yielding significant improvements over the traditional global routing method and the previously used routing flow. Therefore, we conclude that our approaches and results from this thesis are not only theoretically sound but also give compelling results in practice

SALSy: Security-Aware Layout Synthesis

Integrated Circuits (ICs) are the target of diverse attacks during their lifetime. Fabrication-time attacks, such as the insertion of Hardware Trojans, can give an adversary access to privileged data and/or the means to corrupt the IC's internal computation. Post-fabrication attacks, where the end-user takes a malicious role, also attempt to obtain privileged information through means such as fault injection and probing. Taking these threats into account and at the same time, this paper proposes a methodology for Security-Aware Layout Synthesis (SALSy), such that ICs can be designed with security in mind in the same manner as power-performance-area (PPA) metrics are considered today, a concept known as security closure. Furthermore, the trade-offs between PPA and security are considered and a chip is fabricated in a 65nm CMOS commercial technology for validation purposes - a feature not seen in previous research on security closure. Measurements on the fabricated ICs indicate that SALSy promotes a modest increase in power in order to achieve significantly improved security metrics

EVEREST IST - 2002 - 00185 : D23 : final report

Deliverable públic del projecte europeu EVERESTThis deliverable constitutes the final report of the project IST-2002-001858 EVEREST. After its successful completion, the project presents this document that firstly summarizes the context, goal and the approach objective of the project. Then it presents a concise summary of the major goals and results, as well as highlights the most valuable lessons derived form the project work. A list of deliverables and publications is included in the annex.Postprint (published version

Interstellar: Using Halide's Scheduling Language to Analyze DNN Accelerators

We show that DNN accelerator micro-architectures and their program mappings represent specific choices of loop order and hardware parallelism for computing the seven nested loops of DNNs, which enables us to create a formal taxonomy of all existing dense DNN accelerators. Surprisingly, the loop transformations needed to create these hardware variants can be precisely and concisely represented by Halide's scheduling language. By modifying the Halide compiler to generate hardware, we create a system that can fairly compare these prior accelerators. As long as proper loop blocking schemes are used, and the hardware can support mapping replicated loops, many different hardware dataflows yield similar energy efficiency with good performance. This is because the loop blocking can ensure that most data references stay on-chip with good locality and the processing units have high resource utilization. How resources are allocated, especially in the memory system, has a large impact on energy and performance. By optimizing hardware resource allocation while keeping throughput constant, we achieve up to 4.2X energy improvement for Convolutional Neural Networks (CNNs), 1.6X and 1.8X improvement for Long Short-Term Memories (LSTMs) and multi-layer perceptrons (MLPs), respectively.Comment: Published as a conference paper at ASPLOS 202

Driving the Network-on-Chip Revolution to Remove the Interconnect Bottleneck in Nanoscale Multi-Processor Systems-on-Chip

The sustained demand for faster, more powerful chips has been met by the availability of chip manufacturing processes allowing for the integration of increasing numbers of computation units onto a single die. The resulting outcome, especially in the embedded domain, has often been called SYSTEM-ON-CHIP (SoC) or MULTI-PROCESSOR SYSTEM-ON-CHIP (MP-SoC). MPSoC design brings to the foreground a large number of challenges, one of the most prominent of which is the design of the chip interconnection. With a number of on-chip blocks presently ranging in the tens, and quickly approaching the hundreds, the novel issue of how to best provide on-chip communication resources is clearly felt. NETWORKS-ON-CHIPS (NoCs) are the most comprehensive and scalable answer to this design concern. By bringing large-scale networking concepts to the on-chip domain, they guarantee a structured answer to present and future communication requirements. The point-to-point connection and packet switching paradigms they involve are also of great help in minimizing wiring overhead and physical routing issues. However, as with any technology of recent inception, NoC design is still an evolving discipline. Several main areas of interest require deep investigation for NoCs to become viable solutions: • The design of the NoC architecture needs to strike the best tradeoff among performance, features and the tight area and power constraints of the onchip domain. • Simulation and verification infrastructure must be put in place to explore, validate and optimize the NoC performance. • NoCs offer a huge design space, thanks to their extreme customizability in terms of topology and architectural parameters. Design tools are needed to prune this space and pick the best solutions. • Even more so given their global, distributed nature, it is essential to evaluate the physical implementation of NoCs to evaluate their suitability for next-generation designs and their area and power costs. This dissertation performs a design space exploration of network-on-chip architectures, in order to point-out the trade-offs associated with the design of each individual network building blocks and with the design of network topology overall. The design space exploration is preceded by a comparative analysis of state-of-the-art interconnect fabrics with themselves and with early networkon- chip prototypes. The ultimate objective is to point out the key advantages that NoC realizations provide with respect to state-of-the-art communication infrastructures and to point out the challenges that lie ahead in order to make this new interconnect technology come true. Among these latter, technologyrelated challenges are emerging that call for dedicated design techniques at all levels of the design hierarchy. In particular, leakage power dissipation, containment of process variations and of their effects. The achievement of the above objectives was enabled by means of a NoC simulation environment for cycleaccurate modelling and simulation and by means of a back-end facility for the study of NoC physical implementation effects. Overall, all the results provided by this work have been validated on actual silicon layout

The Role of Responsive Pricing in the Internet

The Internet continues to evolve as it reaches out to a wider user population. The recent introduction of user-friendly navigation and retrieval tools for the World Wide Web has triggered an unprecedented level of interest in the Internet among the media and the general public, as well as in the technical community. It seems inevitable that some changes or additions are needed in the control mechanisms used to allocate usage of Internet resources. In this paper, we argue that a feedback signal in the form of a variable price for network service is a workable tool to aid network operators in controlling Internet traffic. We suggest that these prices should vary dynamically based on the current utilization of network resources. We show how this responsive pricing puts control of network service back where it belongs: with the users.Internet, pricing, feedback, networks

Design Issues in Internet 0 Federation

Internet 0 is proposed as a local area network that supports extremely small network devices with very little capacity for computation, storage, or communication. Internet 0 addresses the issue of connecting very small, inexpensive devices such as lightbulbs and heating vents with their controllers. To achieve this effectively, Internet 0 assumes both that operating between communicating end-nodes should not require third-party support, and that IP will be available all the way to those end-nodes. Several simplifying assumptions are made in Internet 0 to achieve this. The objective of this paper is to explore issues of design in a context where federation of an Internet 0 net either with other Internet 0 nets or the global Internet becomes important. The question we ask is whether the end-node in such an Internet 0 needs to know more or behave differently in such a federated environment, and how one might achieve such federation. We explore three aspects of network design in this study: addressing and routing, traffic collision and congestion control, and security. In each case, based on analysis, we conclude that to reach our goals in a generalizable and extensible fashion, a third party service will be needed to act as an intermediary, and propose that a single service should provide all the required federation services.Singapore-MIT Alliance (SMA