Network on Chip for FPGA: Development of a test system for Network on Chip

Testing and verification of digital systems is an essential part of product develop-ment. The Network on Chip(NoC), as a new paradigm within interconnections;has a specific need for testing. This is to determine how performance and prop-erties of the NoC are compared to the requirements of different systems such asprocessors or media applications.A NoC has been developed within the AHEAD project to form a basis for areconfigurable platform used in the AHEAD system. This report gives an outlineof the project to develop testing and benchmarking systems for a NoC. The specificwork has been regarding the development of a generic module connected to theNoC and capability of testing the NoCs properties. The test system was initiatedby Ivar Ersland in 2009 and developed further by Andreas Hepsø, and MagnusNamork in the fall of 2010. The functionality and systems that are implementedare the following: Fully functional Hardware/Software interface which defines communicationbetween NoC the user Reactive system which responds to interaction based on package information MPEG example system that mimics an MPEG data stream Software reconfiguration of the traffic tables by sending specific packages tothe system Cell processor example application to test simple computation and commu-nicating modules on the networkThe systems have been tested successfully, verified and implemented on a XilinxSpartan FPGA. It has also been developed a software system written in C to read and interpret data from the Network in on-chip tests. In total these imple-mentations have been the foundation of building a benchmarking platform for theNoC

Technical alignment

This essay discusses the importance of the areas of infrastructure and testing to help digital preservation services demonstrate reliability, transparency, and accountability. It encourages practitioners to build a strong culture in which transparency and collaborations between technical frameworks are valued highly. It also argues for devising and applying agreed-upon metrics that will enable the systematic analysis of preservation infrastructure. The essay begins by defining technical infrastructure and testing in the digital preservation context, provides case studies that exemplify both progress and challenges for technical alignment in both areas, and concludes with suggestions for achieving greater degrees of technical alignment going forward

Static Torsion Testing and Modeling of a Variable Thickness Hybrid Composite Bull Gear

Torsional strength of a variable thickness hybrid gear web was measured by performing static testing on the part in a large torsion test frame. The outer rim of the hybrid gear web was fixed to the bottom of the test frame and loading was applied to the web through a shaft. The test setup included the installation of digital image correlation (DIC) systems to obtain deformation and strain measurements from the surfaces of the hybrid gear web and the mechanical test equipment to ensure reliability of the test. The results indicated that the variable thickness hybrid gear web achieved approximately twice the torsional strength compared to that of previous hybrid gear designs. The DIC analysis showed significantly more straining of the loading shaft than the actual test article. Additionally, the results demonstrated the importance and affect that the metallic, lobed interlock features had on the principal strain and out-of-plane displacement fields. The analysis revealed that the fixed outer rim was in fact rotating and a rigid body motion compensation (RBMC) function was computed to determine the actual rotation of the hub and composite web relative to the outer rim. Modeling simulations were performed for the variable thickness hybrid gear web and correlated well with the RBMC rotational deformation seen in the DIC analysis. In addition to benchmarking the load capacity of the hybrid gear web, measuring its strength is useful information to define the parameters needed for dynamic, endurance, and other testing of the part

Information Outlook, September 2005

Volume 9, Issue 9https://scholarworks.sjsu.edu/sla_io_2005/1008/thumbnail.jp

Comparisons of the execution times and memory requirements for high-speed discrete fourier transforms and fast fourier transforms, for the measurement of AC power harmonics

Conventional wisdom dictates that a Fast Fourier Transform (FFT) will be a more computationally effective method for measuring multiple harmonics than a Discrete Fourier Transform (DFT) approach. However, in this paper it is shown that carefully coded discrete transforms which distribute their computational load over many frames can be made to produce results in shorter execution times than the FFT approach, even for large number of harmonic measurement frequencies. This is because the execution time of the presented DFT actually rises with N and not the classical N2 value, while the execution time of the FFT rises with Nlog2N

Initial specification of the evaluation tasks "Use cases to bridge validation and benchmarking" PROMISE Deliverable 2.1

Evaluation of multimedia and multilingual information access systems needs to be performed from a usage oriented perspective. This document outlines use cases from the three use case domains of the PROMISE project and gives some initial pointers to how their respective characteristics can be extrapolated to determine and guide evaluation activities, both with respect to benchmarking and to validation of the usage hypotheses. The use cases will be developed further during the course of the evaluation activities and workshops projected to occur in coming CLEF conferences