Obstacle-Avoiding Rectilinear Steiner Minimal Tree Construction

Obstacle-avoiding rectilinear Steiner minimal tree (OARSMT) construction is becoming one of the most sought after problems in modern design flow. In this thesis we present an algorithm to route a multi-terminal net in the presence of obstacles. Ours is a top down approach which includes partitioning the initial solution into subproblems and using obstacle aware version of Fast Lookup Table based Wirelength Estimation (OA-FLUTE) at a lower level to generate an OAST followed by recombining them with some backend refinement. To construct an initial connectivity graph we use a novel obstacle-avoiding spanning graph (OASG) algorithm which is a generalization of Zhou\u27s spanning graph algorithm without obstacle presented in ASPDAC 2001. The runtime complexity of our algorithm is O(n log n)

Routing for analog chip designs at NXP Semiconductors

During the study week 2011 we worked on the question of how to automate certain aspects of the design of analog chips. Here we focused on the task of connecting different blocks with electrical wiring, which is particularly tedious to do by hand. For digital chips there is a wealth of research available for this, as in this situation the amount of blocks makes it hopeless to do the design by hand. Hence, we set our task to finding solutions that are based on the previous research, as well as being tailored to the specific setting given by NXP. This resulted in an heuristic approach, which we presented at the end of the week in the form of a protoype tool. In this report we give a detailed account of the ideas we used, and describe possibilities to extend the approach

Interconnect optimizations for nanometer VLSI design

textAs the semiconductor technology scales into deeper sub-micron domain, billions of transistors can be used on a single system-on-chip (SOC) makes interconnection optimization more important roughly for two reasons. First, congestion, power, timing in routing and buffering requirements make inter- connection optimization more and more challenging. Second, gate delay get- ting shorter while the RC delay gets longer due to scaling. Study of interconnection construction and optimization algorithms in real industry flows and designs ends up with interesting findings. One used to be overlooked but very important and practical problem is how to utilize over- the-block routing resources intelligently. Routing over large IP blocks needs special attention as there is almost no way to insert buffers inside hard IP blocks, which can lead to unsolvable slew/timing violations. In current design flows we have seen, the routing resources over the IP blocks were either dealt as routing blockages leading to a significant waste, or simply treated in the same way as outside-the-block routing resources, which would violate the slew constraints and thus fail buffering. To handle that, this work proposes a novel buffering-aware over-the- block rectilinear Steiner minimum tree (BOB-RSMT) algorithm which helps reclaim the “wasted” over-the-block routing resources while meeting user-specified slew constraints. Proposed algorithm incrementally and efficiently migrates initial tree structures with buffering-awareness to meet slew constraints while minimizing wire-length. Moreover, due to the fact that timing optimization is important for the VLSI design, in this work, timing-driven over-the-block rectilinear Steiner tree (TOB-RST) is also studied to optimize critical paths. This proposed TOB-RST algorithm can be used in routing or post-routing stage to provide high-quality topologies to help close timing. Then a follow-up problem emerges: how to accomplish the whole routing with over-the-block routing resources used properly. Utilizing over-the- block routing resources could dramatically improve the routing solution, yet require special attention, since the slew, affected by different RC on different metal layers, must be constrained by buffering and is easily violated. Moreover, even of all nets are slew-legalized, the routing solution could still suffer from heavy congestion problem. A new global router, BOB-Router, is to solve the over-the-block global routing problem through minimizing overflows, wire-length and via count simultaneously without violating slew constraints. Based on my completed works, BOB-RSMT and BOB-Router tremendously improve the overall routing and buffering quality. Experimental results show that proposed over-the-block rectilinear Steiner tree construction and routing completely satisfies the slew constraints and significantly outperforms the obstacle-avoiding rectilinear Steiner tree construction and routing in terms of wire-length, via count and overflows.Electrical and Computer Engineerin

NN-Steiner: A Mixed Neural-algorithmic Approach for the Rectilinear Steiner Minimum Tree Problem

Recent years have witnessed rapid advances in the use of neural networks to solve combinatorial optimization problems. Nevertheless, designing the "right" neural model that can effectively handle a given optimization problem can be challenging, and often there is no theoretical understanding or justification of the resulting neural model. In this paper, we focus on the rectilinear Steiner minimum tree (RSMT) problem, which is of critical importance in IC layout design and as a result has attracted numerous heuristic approaches in the VLSI literature. Our contributions are two-fold. On the methodology front, we propose NN-Steiner, which is a novel mixed neural-algorithmic framework for computing RSMTs that leverages the celebrated PTAS algorithmic framework of Arora to solve this problem (and other geometric optimization problems). Our NN-Steiner replaces key algorithmic components within Arora's PTAS by suitable neural components. In particular, NN-Steiner only needs four neural network (NN) components that are called repeatedly within an algorithmic framework. Crucially, each of the four NN components is only of bounded size independent of input size, and thus easy to train. Furthermore, as the NN component is learning a generic algorithmic step, once learned, the resulting mixed neural-algorithmic framework generalizes to much larger instances not seen in training. Our NN-Steiner, to our best knowledge, is the first neural architecture of bounded size that has capacity to approximately solve RSMT (and variants). On the empirical front, we show how NN-Steiner can be implemented and demonstrate the effectiveness of our resulting approach, especially in terms of generalization, by comparing with state-of-the-art methods (both neural and non-neural based).Comment: This paper is the complete version with appendix of the paper accepted in AAAI'24 with the same titl

Multi-objective optimal design of obstacle-avoiding two-dimensional Steiner trees with application to ascent assembly engineering.

We present an effective optimization strategy that is capable of discovering high-quality cost-optimal solution for two-dimensional (2D) path network layouts (i.e., groups of obstacle-avoiding Euclidean Steiner trees) that, among other applications, can serve as templates for complete ascent assembly structures (CAA-structures). The main innovative aspect of our approach is that our aim is not restricted to simply synthesizing optimal assembly designs with regard to a given goal, but we also strive to discover the best trade-offs between geometric and domain-dependent optimal designs. As such, the proposed approach is centred on a variably constrained multi-objective formulation of the optimal design task and on an efficient co-evolutionary solver. The results we obtained on both artificial problems and realistic design scenarios based on an industrial test case empirically support the value of our contribution to the fields of optimal obstacle-avoiding path generation in particular and design automation in general

Optimal Flood Control

A mathematical model for optimal control of the water levels in a chain of reservoirs is studied. Some remarks regarding sensitivity with respect to the time horizon, terminal cost and forecast of inflow are made

Computing Shortest Paths in the Plane with Removable Obstacles

We consider the problem of computing a Euclidean shortest path in the presence of removable obstacles in the plane. In particular, we have a collection of pairwise-disjoint polygonal obstacles, each of which may be removed at some cost c_i > 0. Given a cost budget C > 0, and a pair of points s, t, which obstacles should be removed to minimize the path length from s to t in the remaining workspace? We show that this problem is NP-hard even if the obstacles are vertical line segments. Our main result is a fully-polynomial time approximation scheme (FPTAS) for the case of convex polygons. Specifically, we compute an (1 + epsilon)-approximate shortest path in time O({nh}/{epsilon^2} log n log n/epsilon) with removal cost at most (1+epsilon)C, where h is the number of obstacles, n is the total number of obstacle vertices, and epsilon in (0, 1) is a user-specified parameter. Our approximation scheme also solves a shortest path problem for a stochastic model of obstacles, where each obstacle\u27s presence is an independent event with a known probability. Finally, we also present a data structure that can answer s-t path queries in polylogarithmic time, for any pair of points s, t in the plane

The Steiner Ratio for the Obstacle-Avoiding Steiner Tree Problem

This thesis examines the (geometric) Steiner tree problem: Given a set of points P in the plane, find a shortest tree interconnecting all points in P, with the possibility of adding points outside P, called the Steiner points, as additional vertices of the tree. The Steiner tree problem has been studied in different metric spaces. In this thesis, we study the problem in Euclidean and rectilinear metrics. One of the most natural heuristics for the Steiner tree problem is to use a minimum spanning tree, which can be found in O(nlogn) time . The performance ratio of this heuristic is given by the Steiner ratio, which is defined as the minimum possible ratio between the lengths of a minimum Steiner tree and a minimum spanning tree. We survey the background literature on the Steiner ratio and study the generalization of the Steiner ratio to the case of obstacles. We introduce the concept of an anchored Steiner tree: an obstacle-avoiding Steiner tree in which the Steiner points are only allowed at obstacle corners. We define the obstacle-avoiding Steiner ratio as the ratio of the length of an obstacle-avoiding minimum Steiner tree to that of an anchored obstacle-avoiding minimum Steiner tree. We prove that, for the rectilinear metric, the obstacle-avoiding Steiner ratio is equal to the traditional (obstacle-free) Steiner ratio. We conjecture that this is also the case for the Euclidean metric and we prove this conjecture for three points and any number of obstacles

Obstacle-avoiding rectilinear Steiner tree.

Li, Liang.Thesis (M.Phil.)--Chinese University of Hong Kong, 2009.Includes bibliographical references (leaves 57-61).Abstract also in Chinese.Abstract --- p.iAcknowledgement --- p.ivChapter 1 --- Introduction --- p.1Chapter 1.1 --- Background --- p.1Chapter 1.1.1 --- Partitioning --- p.1Chapter 1.1.2 --- Floorplanning and Placement --- p.2Chapter 1.1.3 --- Routing --- p.2Chapter 1.1.4 --- Compaction --- p.3Chapter 1.2 --- Motivations --- p.3Chapter 1.3 --- Problem Formulation --- p.4Chapter 1.3.1 --- Properties of OARSMT --- p.4Chapter 1.4 --- Progress on the Problem --- p.4Chapter 1.5 --- Contributions --- p.5Chapter 1.6 --- Thesis Organization --- p.6Chapter 2 --- Literature Review on OARSMT --- p.8Chapter 2.1 --- Introduction --- p.8Chapter 2.2 --- Previous Methods --- p.9Chapter 2.2.1 --- OARSMT --- p.9Chapter 2.2.2 --- Shortest Path Problem with Blockages --- p.13Chapter 2.2.3 --- OARSMT with Delay Minimization --- p.14Chapter 2.2.4 --- OARSMT with Worst Negative Slack Maximization --- p.14Chapter 2.3 --- Comparison --- p.15Chapter 3 --- Heuristic Method --- p.17Chapter 3.1 --- Introduction --- p.17Chapter 3.2 --- Our Approach --- p.18Chapter 3.2.1 --- Handling of Multi-pin Nets --- p.18Chapter 3.2.2 --- Propagation --- p.20Chapter 3.2.3 --- Backtrack --- p.23Chapter 3.2.4 --- Finding MST --- p.26Chapter 3.2.5 --- Local Refinement Scheme --- p.26Chapter 3.3 --- Experimental Results --- p.28Chapter 3.4 --- Summary --- p.28Chapter 4 --- Exact Method --- p.32Chapter 4.1 --- Introduction --- p.32Chapter 4.2 --- Review on GeoSteiner --- p.33Chapter 4.3 --- Overview of our Approach --- p.33Chapter 4.4 --- FST with Virtual Pins --- p.34Chapter 4.4.1 --- Definition of FST --- p.34Chapter 4.4.2 --- Notations --- p.36Chapter 4.4.3 --- Properties of FST with Virtual Pins --- p.36Chapter 4.5 --- Generation of FST with Virtual Pins --- p.46Chapter 4.5.1 --- Generation of FST with Two Pins --- p.46Chapter 4.5.2 --- Generation of FST with 3 or More Pins --- p.48Chapter 4.6 --- Concatenation of FSTs with Virtual Pins --- p.50Chapter 4.7 --- Experimental Results --- p.52Chapter 4.8 --- Summary --- p.53Chapter 5 --- Conclusion --- p.55Bibliography --- p.6