Obstacle-Avoiding Rectilinear Steiner Minimal Tree Construction

Obstacle-avoiding rectilinear Steiner minimal tree (OARSMT) construction is becoming one of the most sought after problems in modern design flow. In this thesis we present an algorithm to route a multi-terminal net in the presence of obstacles. Ours is a top down approach which includes partitioning the initial solution into subproblems and using obstacle aware version of Fast Lookup Table based Wirelength Estimation (OA-FLUTE) at a lower level to generate an OAST followed by recombining them with some backend refinement. To construct an initial connectivity graph we use a novel obstacle-avoiding spanning graph (OASG) algorithm which is a generalization of Zhou\u27s spanning graph algorithm without obstacle presented in ASPDAC 2001. The runtime complexity of our algorithm is O(n log n)

Optimal Flood Control

A mathematical model for optimal control of the water levels in a chain of reservoirs is studied. Some remarks regarding sensitivity with respect to the time horizon, terminal cost and forecast of inflow are made

Transportation networks inspired by leaf venation algorithms

Copyright IoP publishingBiological systems have adapted to environmental constraints and limited resource availability. In the present study, we evaluate the algorithm underlying leaf venation (LV) deployment using graph theory. We compare the traffic balance, travel and cost efficiency of simply-connected LV networks to those of the fan tree and of the spanning tree. We use a Pareto front to show that the total length of leaf venations is close to optimal. Then we apply the LV algorithm to design transportation networks in the city of Atlanta. Results show that leaf-inspired models can perform similarly or better than computer-intensive optimization algorithms in terms of network cost and service performance, which could facilitate the design of engineering transportation networks

Routing for analog chip designs at NXP Semiconductors

During the study week 2011 we worked on the question of how to automate certain aspects of the design of analog chips. Here we focused on the task of connecting different blocks with electrical wiring, which is particularly tedious to do by hand. For digital chips there is a wealth of research available for this, as in this situation the amount of blocks makes it hopeless to do the design by hand. Hence, we set our task to finding solutions that are based on the previous research, as well as being tailored to the specific setting given by NXP. This resulted in an heuristic approach, which we presented at the end of the week in the form of a protoype tool. In this report we give a detailed account of the ideas we used, and describe possibilities to extend the approach

Obstacle-avoiding rectilinear Steiner tree.

Li, Liang.Thesis (M.Phil.)--Chinese University of Hong Kong, 2009.Includes bibliographical references (leaves 57-61).Abstract also in Chinese.Abstract --- p.iAcknowledgement --- p.ivChapter 1 --- Introduction --- p.1Chapter 1.1 --- Background --- p.1Chapter 1.1.1 --- Partitioning --- p.1Chapter 1.1.2 --- Floorplanning and Placement --- p.2Chapter 1.1.3 --- Routing --- p.2Chapter 1.1.4 --- Compaction --- p.3Chapter 1.2 --- Motivations --- p.3Chapter 1.3 --- Problem Formulation --- p.4Chapter 1.3.1 --- Properties of OARSMT --- p.4Chapter 1.4 --- Progress on the Problem --- p.4Chapter 1.5 --- Contributions --- p.5Chapter 1.6 --- Thesis Organization --- p.6Chapter 2 --- Literature Review on OARSMT --- p.8Chapter 2.1 --- Introduction --- p.8Chapter 2.2 --- Previous Methods --- p.9Chapter 2.2.1 --- OARSMT --- p.9Chapter 2.2.2 --- Shortest Path Problem with Blockages --- p.13Chapter 2.2.3 --- OARSMT with Delay Minimization --- p.14Chapter 2.2.4 --- OARSMT with Worst Negative Slack Maximization --- p.14Chapter 2.3 --- Comparison --- p.15Chapter 3 --- Heuristic Method --- p.17Chapter 3.1 --- Introduction --- p.17Chapter 3.2 --- Our Approach --- p.18Chapter 3.2.1 --- Handling of Multi-pin Nets --- p.18Chapter 3.2.2 --- Propagation --- p.20Chapter 3.2.3 --- Backtrack --- p.23Chapter 3.2.4 --- Finding MST --- p.26Chapter 3.2.5 --- Local Refinement Scheme --- p.26Chapter 3.3 --- Experimental Results --- p.28Chapter 3.4 --- Summary --- p.28Chapter 4 --- Exact Method --- p.32Chapter 4.1 --- Introduction --- p.32Chapter 4.2 --- Review on GeoSteiner --- p.33Chapter 4.3 --- Overview of our Approach --- p.33Chapter 4.4 --- FST with Virtual Pins --- p.34Chapter 4.4.1 --- Definition of FST --- p.34Chapter 4.4.2 --- Notations --- p.36Chapter 4.4.3 --- Properties of FST with Virtual Pins --- p.36Chapter 4.5 --- Generation of FST with Virtual Pins --- p.46Chapter 4.5.1 --- Generation of FST with Two Pins --- p.46Chapter 4.5.2 --- Generation of FST with 3 or More Pins --- p.48Chapter 4.6 --- Concatenation of FSTs with Virtual Pins --- p.50Chapter 4.7 --- Experimental Results --- p.52Chapter 4.8 --- Summary --- p.53Chapter 5 --- Conclusion --- p.55Bibliography --- p.6

Planeación óptima de redes de distribución eléctrica aérea usando métodos heurísticos y procesos de simulación.

This article is intended a planning model for the deployment of the overhead electrical distribution systems, which allows under heuristics and optimization criteria to reduce the cost of resources associated in the construction of the network; it shows an optimal deployment of distribution transformers considering technical restriction and capacity. The model presents warm a routing on a geo-referenced scenery with information from the OpenStreetMap platform, with the purpose that the topology of the net is under real condition and design of a city; furthermore, the minimum Steiner tree is used for the overhead distribution network. Additionally, the model attaches of scalability and flexibility principles, adjusting the results to variations in different scenarios. On the other hand, with Cymdist software simulation verified the electrical parameters to involved in the design of overhead network. Results obtained present for electrification companies a reference points for future planning of the electricity distribution networks, adapting to the random changes in demand.En este artículo se plantea un modelo de planeación para despliegue de los sistemas aéreos de distribución eléctrica, el cual permita bajo criterios heurísticos y de optimización reducir los costos asociados a los recursos empleados en la construcción de la red; muestra un despliegue óptimo de transformadores de distribución considerando restricciones técnicas y de capacidad. Se advierte que el modelo presenta un enrutamiento sobre un escenario georreferenciado con información obtenida de la plataforma OpenStreetMap, con el propósito de que la topología de la red sea bajo condiciones reales y de diseño de una ciudad; por otro lado, se hace uso del árbol mínimo de Steiner para el emplazamiento de la red aérea de distribución. Adicionalmente el modelo adjunta los principios de escalabilidad y flexibilidad, ajustando los resultados a las variaciones en distintos escenarios. En una segunda instancia con el software de simulación Cymdist se verifica el comportamiento de los parámetros eléctricos implicados en el diseño de las redes aéreas. Los resultados obtenidos presentan a las empresas de electrificación puntos de referencia para las futuras planificaciones de las redes eléctricas de distribución adaptándose a los cambios aleatorios de la demanda

Interconnect optimizations for nanometer VLSI design

textAs the semiconductor technology scales into deeper sub-micron domain, billions of transistors can be used on a single system-on-chip (SOC) makes interconnection optimization more important roughly for two reasons. First, congestion, power, timing in routing and buffering requirements make inter- connection optimization more and more challenging. Second, gate delay get- ting shorter while the RC delay gets longer due to scaling. Study of interconnection construction and optimization algorithms in real industry flows and designs ends up with interesting findings. One used to be overlooked but very important and practical problem is how to utilize over- the-block routing resources intelligently. Routing over large IP blocks needs special attention as there is almost no way to insert buffers inside hard IP blocks, which can lead to unsolvable slew/timing violations. In current design flows we have seen, the routing resources over the IP blocks were either dealt as routing blockages leading to a significant waste, or simply treated in the same way as outside-the-block routing resources, which would violate the slew constraints and thus fail buffering. To handle that, this work proposes a novel buffering-aware over-the- block rectilinear Steiner minimum tree (BOB-RSMT) algorithm which helps reclaim the “wasted” over-the-block routing resources while meeting user-specified slew constraints. Proposed algorithm incrementally and efficiently migrates initial tree structures with buffering-awareness to meet slew constraints while minimizing wire-length. Moreover, due to the fact that timing optimization is important for the VLSI design, in this work, timing-driven over-the-block rectilinear Steiner tree (TOB-RST) is also studied to optimize critical paths. This proposed TOB-RST algorithm can be used in routing or post-routing stage to provide high-quality topologies to help close timing. Then a follow-up problem emerges: how to accomplish the whole routing with over-the-block routing resources used properly. Utilizing over-the- block routing resources could dramatically improve the routing solution, yet require special attention, since the slew, affected by different RC on different metal layers, must be constrained by buffering and is easily violated. Moreover, even of all nets are slew-legalized, the routing solution could still suffer from heavy congestion problem. A new global router, BOB-Router, is to solve the over-the-block global routing problem through minimizing overflows, wire-length and via count simultaneously without violating slew constraints. Based on my completed works, BOB-RSMT and BOB-Router tremendously improve the overall routing and buffering quality. Experimental results show that proposed over-the-block rectilinear Steiner tree construction and routing completely satisfies the slew constraints and significantly outperforms the obstacle-avoiding rectilinear Steiner tree construction and routing in terms of wire-length, via count and overflows.Electrical and Computer Engineerin

NN-Steiner: A Mixed Neural-algorithmic Approach for the Rectilinear Steiner Minimum Tree Problem

Recent years have witnessed rapid advances in the use of neural networks to solve combinatorial optimization problems. Nevertheless, designing the "right" neural model that can effectively handle a given optimization problem can be challenging, and often there is no theoretical understanding or justification of the resulting neural model. In this paper, we focus on the rectilinear Steiner minimum tree (RSMT) problem, which is of critical importance in IC layout design and as a result has attracted numerous heuristic approaches in the VLSI literature. Our contributions are two-fold. On the methodology front, we propose NN-Steiner, which is a novel mixed neural-algorithmic framework for computing RSMTs that leverages the celebrated PTAS algorithmic framework of Arora to solve this problem (and other geometric optimization problems). Our NN-Steiner replaces key algorithmic components within Arora's PTAS by suitable neural components. In particular, NN-Steiner only needs four neural network (NN) components that are called repeatedly within an algorithmic framework. Crucially, each of the four NN components is only of bounded size independent of input size, and thus easy to train. Furthermore, as the NN component is learning a generic algorithmic step, once learned, the resulting mixed neural-algorithmic framework generalizes to much larger instances not seen in training. Our NN-Steiner, to our best knowledge, is the first neural architecture of bounded size that has capacity to approximately solve RSMT (and variants). On the empirical front, we show how NN-Steiner can be implemented and demonstrate the effectiveness of our resulting approach, especially in terms of generalization, by comparing with state-of-the-art methods (both neural and non-neural based).Comment: This paper is the complete version with appendix of the paper accepted in AAAI'24 with the same titl

Multi-objective optimal design of obstacle-avoiding two-dimensional Steiner trees with application to ascent assembly engineering.

We present an effective optimization strategy that is capable of discovering high-quality cost-optimal solution for two-dimensional (2D) path network layouts (i.e., groups of obstacle-avoiding Euclidean Steiner trees) that, among other applications, can serve as templates for complete ascent assembly structures (CAA-structures). The main innovative aspect of our approach is that our aim is not restricted to simply synthesizing optimal assembly designs with regard to a given goal, but we also strive to discover the best trade-offs between geometric and domain-dependent optimal designs. As such, the proposed approach is centred on a variably constrained multi-objective formulation of the optimal design task and on an efficient co-evolutionary solver. The results we obtained on both artificial problems and realistic design scenarios based on an industrial test case empirically support the value of our contribution to the fields of optimal obstacle-avoiding path generation in particular and design automation in general