Delay test for diagnosis of power switches

Power switches are used as part of power-gating technique to reduce leakage power of a design. To the best of our knowledge, this is the first work in open-literature to show a systematic diagnosis method for accurately diagnosingpower switches. The proposed diagnosis method utilizes recently proposed DFT solution for efficient testing of power switches in the presence of PVT variation. It divides power switches into segments such that any faulty power switch is detectable thereby achieving high diagnosis accuracy. The proposed diagnosis method has been validated through SPICE simulation using a number of ISCAS benchmarks synthesized with a 90-nm gate library. Simulation results show that when considering the influence of process variation, the worst case loss of accuracy is less than 4.5%; and the worst case loss of accuracy is less than 12% when considering VT (Voltage and Temperature) variations

Ultra-Low Leakage, Energy-Efficient Digital Integrated Circuit and System Design

The advances of the complementary metal-oxide-semiconductor (CMOS) technology manufacturing and design over the years have enabled a diverse range of applications across the power consumption, performance, and area (PPA) spectra. Many of the recent and prospective applications rely on the availability of energy-autonomous, miniaturized systems, i.e., ultra-low power (ULP) VLSI systems, which are generally characterized by extreme resource limitations. Some examples of applications are wireless sensing platforms, body-area sensor networks (BASN), biomedical and implantable devices, wearables, hearables, and monitors. Within the context of such applications, the key requirements are long lifetime and miniaturized size (sub-/millimeter-scale). In order to enable both requirements, energy-efficiency is the key metric. It allows for extended battery lifetime and operation with the energy that can be harvested from the environment, and it limits the size (volume) of the energy sources utilized to power these systems. Ultra-low voltage (ULV) operation is a key technique in which the VDD of circuits is reduced from nominal to near or below the threshold voltage of the transistor. It is a powerful knob that has been largely exploited by designers in order to achieve ultra-low power consumption and high energy-efficiency in CMOS. Existing ULP VLSI systems typically operate at a lower supply voltage thereby reducing their energy consumption by one to two orders of magnitude in order to enable the aforementioned applications. While supply voltage scaling is a promising measure for achieving low power and reducing energy consumption, it brings up several challenges. One critical issue is the leakage energy dissipated by the devices, which is magnified in portion to the total energy consumption at ULV. The reason is that, as VDD scales from nominal to near-threshold and sub-threshold, transistors become increasingly slower and they accumulate more leakage (i.e., static) power over longer cycle times. This energy waste accounts for a significant portion of the system's total energy consumption, offsets the gains provided by voltage scaling, defines the minimum energy per operation, and poses a practical limit for the system's energy-efficiency. This thesis presents selected research works on ultra-low leakage, energy-efficient digital integrated circuit design. More specifically, it describes novel and key techniques for minimizing the energy waste of idle/underutilized and always-on hardware. The main goal of such techniques is to push the envelope of energy-efficiency in energy-autonomous, miniaturized VLSI systems. Such techniques are applied to key building blocks of emerging mobile and embedded computing devices resulting in state-of-the-art energy-efficiencies

Neural Mechanisms of Drosophila Circadian Rhythms

Animals show circadian rhythms in a variety of physiological functions and behaviors. In Drosophila melanogaster, behavioral rhythms are driven by circadian clock genes that are oscillating in ~150 circadian pacemaker neurons. To explain how circadian neurons encode time and regulate different behavioral rhythms, I performed 24-hour in vivo whole-brain calcium imaging using light-sheet microscopy. First, I found that different groups of circadian neurons show circadian rhythms in spontaneous neural activity with diverse phases. The neural activity phases of the M and E pacemaker groups, which are associated with the morning and evening locomotor activities respectively, occur ~4 hours before their respective behaviors. I also showed that neural activity rhythms are generated by circadian clock gene oscillations, which regulate the expression of IP3R and T-type calcium channels. Next, I asked how the diverse phases of neural activity are generated from the in-phase clock gene oscillations. Groups of circadian neurons inhibit each other via long-duration neuromodulation, mediated by neuropeptides PDF and sNPF, such that their activity phases are properly staggered across the day and night. Certain activity phases are also regulated by environmental light inputs. I then identified an output pathway by which circadian neurons regulate the locomotor activity rhythm. M and E pacemaker groups independently activate a common pre-motor center (termed ellipsoid body ring neurons) through the agency of specific dopaminergic interneurons. Finally, using methods including whole-brain pan-neuronal imaging, I further identified several output circuits downstream of circadian neurons. Circadian neural activity rhythms propagate through these circuits to regulate different behavioral outputs including sleep, olfaction, mating, and feeding rhythms. Together, my findings show how circadian clocks regulate diverse behavioral outputs by two steps; first, circadian clock genes generate diverse circadian neural activity rhythms within a network of interacting pacemaker neurons; then, sequentially-active pacemaker neurons independently and together regulate diverse behavioral outputs by generating diverse circadian neural activity rhythms in different downstream output circuits

CAD Tools for Synthesis of Sleep Convention Logic

This dissertation proposes an automated flow for the Sleep Convention Logic (SCL) asynchronous design style. The proposed flow synthesizes synchronous RTL into an SCL netlist. The flow utilizes commercial design tools, while supplementing missing functionality using custom tools. A method for determining the performance bottleneck in an SCL design is proposed. A constraint-driven method to increase the performance of linear SCL pipelines is proposed. Several enhancements to SCL are proposed, including techniques to reduce the number of registers and total sleep capacitance in an SCL design

Robust low-power digital circuit design in nano-CMOS technologies

Device scaling has resulted in large scale integrated, high performance, low-power, and low cost systems. However the move towards sub-100 nm technology nodes has increased variability in device characteristics due to large process variations. Variability has severe implications on digital circuit design by causing timing uncertainties in combinational circuits, degrading yield and reliability of memory elements, and increasing power density due to slow scaling of supply voltage. Conventional design methods add large pessimistic safety margins to mitigate increased variability, however, they incur large power and performance loss as the combination of worst cases occurs very rarely. In-situ monitoring of timing failures provides an opportunity to dynamically tune safety margins in proportion to on-chip variability that can significantly minimize power and performance losses. We demonstrated by simulations two delay sensor designs to detect timing failures in advance that can be coupled with different compensation techniques such as voltage scaling, body biasing, or frequency scaling to avoid actual timing failures. Our simulation results using 45 nm and 32 nm technology BSIM4 models indicate significant reduction in total power consumption under temperature and statistical variations. Future work involves using dual sensing to avoid useless voltage scaling that incurs a speed loss. SRAM cache is the first victim of increased process variations that requires handcrafted design to meet area, power, and performance requirements. We have proposed novel 6 transistors (6T), 7 transistors (7T), and 8 transistors (8T)-SRAM cells that enable variability tolerant and low-power SRAM cache designs. Increased sense-amplifier offset voltage due to device mismatch arising from high variability increases delay and power consumption of SRAM design. We have proposed two novel design techniques to reduce offset voltage dependent delays providing a high speed low-power SRAM design. Increasing leakage currents in nano-CMOS technologies pose a major challenge to a low-power reliable design. We have investigated novel segmented supply voltage architecture to reduce leakage power of the SRAM caches since they occupy bulk of the total chip area and power. Future work involves developing leakage reduction methods for the combination logic designs including SRAM peripherals

Zuverlässige und Energieeffiziente gemischt-kritische Echtzeit On-Chip Systeme

Multi- and many-core embedded systems are increasingly becoming the target for many applications that require high performance under varying conditions. A resulting challenge is the control, and reliable operation of such complex multiprocessing architectures under changes, e.g., high temperature and degradation. In mixed-criticality systems where many applications with varying criticalities are consolidated on the same execution platform, fundamental isolation requirements to guarantee non-interference of critical functions are crucially important. While Networks-on-Chip (NoCs) are the prevalent solution to provide scalable and efficient interconnects for the multiprocessing architectures, their associated energy consumption has immensely increased. Specifically, hard real-time NoCs must manifest limited energy consumption as thermal runaway in such a core shared resource jeopardizes the whole system guarantees. Thus, dynamic energy management of NoCs, as opposed to the related work static solutions, is highly necessary to save energy and decrease temperature, while preserving essential temporal requirements. In this thesis, we introduce a centralized management to provide energy-aware NoCs for hard real-time systems. The design relies on an energy control network, developed on top of an existing switch arbitration network to allow isolation between energy optimization and data transmission. The energy control layer includes local units called Power-Aware NoC controllers that dynamically optimize NoC energy depending on the global state and applications’ temporal requirements. Furthermore, to adapt to abnormal situations that might occur in the system due to degradation, we extend the concept of NoC energy control to include the entire system scope. That is, online resource management employing hierarchical control layers to treat system degradation (imminent core failures) is supported. The mechanism applies system reconfiguration that involves workload migration. For mixed-criticality systems, it allows flexible boundaries between safety-critical and non-critical subsystems to safely apply the reconfiguration, preserving fundamental safety requirements and temporal predictability. Simulation and formal analysis-based experiments on various realistic usecases and benchmarks are conducted showing significant improvements in NoC energy-savings and in treatment of system degradation for mixed-criticality systems improving dependability over the status quo.Eingebettete Many- und Multi-core-Systeme werden zunehmend das Ziel für Anwendungen, die hohe Anfordungen unter unterschiedlichen Bedinungen haben. Für solche hochkomplexed Multi-Prozessor-Systeme ist es eine grosse Herausforderung zuverlässigen Betrieb sicherzustellen, insbesondere wenn sich die Umgebungseinflüsse verändern. In Systeme mit gemischter Kritikalität, in denen viele Anwendungen mit unterschiedlicher Kritikalität auf derselben Ausführungsplattform bedient werden müssen, sind grundlegende Isolationsanforderungen zur Gewährleistung der Nichteinmischung kritischer Funktionen von entscheidender Bedeutung. Während On-Chip Netzwerke (NoCs) häufig als skalierbare Verbindung für die Multiprozessor-Architekturen eingesetzt werden, ist der damit verbundene Energieverbrauch immens gestiegen. Daher sind dynamische Plattformverwaltungen, im Gegensatz zu den statischen, zwingend notwendig, um ein System an die oben genannten Veränderungen anzupassen und gleichzeitig Timing zu gewährleisten. In dieser Arbeit entwickeln wir energieeffiziente NoCs für harte Echtzeitsysteme. Das Design basiert auf einem Energiekontrollnetzwerk, das auf einem bestehenden Switch-Arbitration-Netzwerk entwickelt wurde, um eine Isolierung zwischen Energieoptimierung und Datenübertragung zu ermöglichen. Die Energiesteuerungsschicht umfasst lokale Einheiten, die als Power-Aware NoC-Controllers bezeichnet werden und die die NoC-Energie in Abhängigkeit vom globalen Zustand und den zeitlichen Anforderungen der Anwendungen optimieren. Darüber hinaus wird das Konzept der NoC-Energiekontrolle zur Anpassung an Anomalien, die aufgrund von Abnutzung auftreten können, auf den gesamten Systemumfang ausgedehnt. Online- Ressourcenverwaltungen, die hierarchische Kontrollschichten zur Behandlung Abnutzung (drohender Kernausfälle) einsetzen, werden bereitgestellt. Bei Systemen mit gemischter Kritikalität erlaubt es flexible Grenzen zwischen sicherheitskritischen und unkritischen Subsystemen, um die Rekonfiguration sicher anzuwenden, wobei grundlegende Sicherheitsanforderungen erhalten bleiben und Timing Vorhersehbarkeit. Experimente werden auf der Basis von Simulationen und formalen Analysen zu verschiedenen realistischen Anwendungsfallen und Benchmarks durchgeführt, die signifikanten Verbesserungen bei On-Chip Netzwerke-Energieeinsparungen und bei der Behandlung von Abnutzung für Systeme mit gemischter Kritikalität zur Verbesserung die Systemstabilität gegenüber dem bisherigen Status quo zeigen

Connectivity, Organization, and Network Coordination of the Drosophila Central Circadian Clock.

Daily rhythms in behavior and physiology are orchestrated by a network of circadian clock neurons. Neuronal connections within this network produce coherence and robustness in circadian timekeeping that are uncharacteristic of rhythms driven by non-neuronal clocks. Using Drosophila as a model system, my thesis research aims to understand how clock neurons are physiologically connected and how their molecular oscillations are coordinated to produce coherent circadian rhythms. I have developed an experimental approach to address functional connectivity in the fly brain that combines chemogenetic excitation of neurons of interest with simultaneous monitoring of potential postsynaptic physiology with genetically encoded fluorescent sensors. Using this method, I have mapped connections in the clock network mediated by the critical neuropeptide Pigment-Dispersing Factor. In addition, I have performed ex vivo patch-clamp recordings of the fly clock neurons and provided the first electrophysiological characterization of the dorsal lateral neurons (LNds), the Evening Oscillator of the clock network. I find that the neuronal activity LNds is modulated by multiple fast neurotransmitters, and that a group of dorsal clock neurons provides inhibitory synaptic input onto the LNds. Furthermore, I find that while GABAergic inhibition of the clock network promotes sleep at night, glutamatergic inhibition promotes wakefulness during the day. To study how the molecular rhythms of clock neurons are coordinated, I have genetically sped-up or slowed-down the molecular clock in specific subsets of clock neurons and determined how such manipulations affect the molecular oscillations in un-manipulated clock neuron classes and sleep/activity rhythms. I find that the various groups of clock neurons do not display uniform modes of coupling. Rather, they display unique and complex coupling relationships that vary from group to group. In contrast to the widely accepted “Master Pacemaker” model, my results show that the clock network consists of multiple independent oscillators, each unified by its neuropeptide output. Lastly, I find that robust circadian rhythms require coherence of molecular clocks across a much larger proportion of the clock network than previously thought. Collectively, my thesis research greatly advances our understanding of how the circadian clock neuron network is wired and how it is organized and coordinated.PhDMolecular, Cellular and Developmental BiologyUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/133295/1/zepenyao_1.pd

Uppers and Downers: Understanding Sleep Regulation Using Small Molecules in Drosophila

Sleep is an important physiological state, but its function and regulation remain elusive. In Drosophila melanogaster, a useful model organism for studying sleep, forward genetic screens have identified important sleep-modulating genes and pathways; however, the results of such screens may be limited by developmental abnormalities or lethality associated with mutation of certain genes. To circumvent these limitations, we screened 1280 small molecules for effects on sleep in adult Drosophila. We used genetic and molecular approaches to elucidate the mechanisms by which two of these drugs altered sleep behavior. We found that administration of reserpine, a small molecule inhibitor of the vesicular monoamine transporter (VMAT) that repackages monoamines into presynaptic vesicles, resulted in an increase in sleep. We found that VMAT-null mutants, like reserpine-fed flies, have an increased sleep phenotype, as well as an increased arousal threshold and resistance to the effects of reserpine. However, although the VMAT mutants are consistently resistant to reserpine, other aspects of their sleep phenotype are dependent on genetic background. Thus, they may not have been detected in a classical forward genetic screen, further attesting to the utility of a small molecule screen. Mutations affecting single monoamine pathways did not affect reserpine sensitivity, suggesting that effects of VMAT/reserpine on sleep are mediated by multiple monoamines. We also studied the mode of action of caffeine, a common wake-promoting compound. Caffeine is thought to promote wake by inhibiting adenosine receptors, however previous work demonstrated that the wake-promoting effects of caffeine are independent of the adenosine receptor in the fly. We show that dopamine is required for the wake-promoting effect of caffeine in the fly, and that caffeine likely acts presynaptically to increase dopamine signaling. We identify a cluster of neurons, the paired anterior medial (PAM) cluster of dopaminergic neurons, which are essential for the caffeine response and which show increased activity following caffeine administration. Overall, we find that small molecule screens can be used effectively to identify regulators of adult behavior. The results of our screen and follow-up experiments demonstrate that presynaptic modulation of monoamine signaling may be a major source of sleep regulation