Computing observability don't cares efficiently through polarization

A new method is presented to compute the exact observability don't cares (ODCs) for multiple-level combinational circuits. A new mathematical concept, called polarization, is introduced. Polarization captures the essence of ODC calculation on the otherwise difficult points of reconvergence. It makes it possible to derive the ODC of a node from the ODCs of its fanouts with a very simple formula. Experimental results for the 39 largest MCNC benchmark examples show that the method is able to compute the ODC set (expressed as a Boolean network) for all but one circuit in at most a few second

A Minimum Cut Based Re-synthesis Approach

A new re-synthesis approach that benefits from min-cut based partitioning is proposed. This divide and conquer approach is shown to improve the performance of existing synthesis tools on a variety of benchmarks

Approximate logic circuits: Theory and applications

CMOS technology scaling, the process of shrinking transistor dimensions based on Moore's law, has been the thrust behind increasingly powerful integrated circuits for over half a century. As dimensions are scaled to few tens of nanometers, process and environmental variations can significantly alter transistor characteristics, thus degrading reliability and reducing performance gains in CMOS designs with technology scaling. Although design solutions proposed in recent years to improve reliability of CMOS designs are power-efficient, the performance penalty associated with these solutions further reduces performance gains with technology scaling, and hence these solutions are not well-suited for high-performance designs. This thesis proposes approximate logic circuits as a new logic synthesis paradigm for reliable, high-performance computing systems. Given a specification, an approximate logic circuit is functionally equivalent to the given specification for a "significant" portion of the input space, but has a smaller delay and power as compared to a circuit implementation of the original specification. This contributions of this thesis include (i) a general theory of approximation and efficient algorithms for automated synthesis of approximations for unrestricted random logic circuits, (ii) logic design solutions based on approximate circuits to improve reliability of designs with negligible performance penalty, and (iii) efficient decomposition algorithms based on approxiiii mate circuits to improve performance of designs during logic synthesis. This thesis concludes with other potential applications of approximate circuits and identifies. open problems in logic decomposition and approximate circuit synthesis

Analysis of Hardware Descriptions

The design process for integrated circuits requires a lot of analysis of circuit descriptions. An important class of analyses determines how easy it will be to determine if a physical component suffers from any manufacturing errors. As circuit complexities grow rapidly, the problem of testing circuits also becomes increasingly difficult. This thesis explores the potential for analysing a recent high level hardware description language called Ruby. In particular, we are interested in performing testability analyses of Ruby circuit descriptions. Ruby is ammenable to algebraic manipulation, so we have sought transformations that improve testability while preserving behaviour. The analysis of Ruby descriptions is performed by adapting a technique called abstract interpretation. This has been used successfully to analyse functional programs. This technique is most applicable where the analysis to be captured operates over structures isomorphic to the structure of the circuit. Many digital systems analysis tools require the circuit description to be given in some special form. This can lead to inconsistency between representations, and involves additional work converting between representations. We propose using the original description medium, in this case Ruby, for performing analyses. A related technique, called non-standard interpretation, is shown to be very useful for capturing many circuit analyses. An implementation of a system that performs non-standard interpretation forms the central part of the work. This allows Ruby descriptions to be analysed using alternative interpretations such test pattern generation and circuit layout interpretations. This system follows a similar approach to Boute's system semantics work and O'Donnell's work on Hydra. However, we have allowed a larger class of interpretations to be captured and offer a richer description language. The implementation presented here is constructed to allow a large degree of code sharing between different analyses. Several analyses have been implemented including simulation, test pattern generation and circuit layout. Non-standard interpretation provides a good framework for implementing these analyses. A general model for making non-standard interpretations is presented. Combining forms that combine two interpretations to produce a new interpretation are also introduced. This allows complex circuit analyses to be decomposed in a modular manner into smaller circuit analyses which can be built independently

Automated synthesis and optimization of multilevel logic circuits.

With the increased complexity of Very Large Scaled Integrated (VLSI) circuits, multilevellogic synthesis plays an even more important role due to its flexibility and compactness.The history of symbolic logic and some typical techniques for multilevel logic synthesisare reviewed. These methods include algorithmic approach; Rule-Based approach; BinaryDecision Diagram (BDD) approach; Field Programmable Gate Array(FPGA) approachand several perturbation applications.One new kind of don't cares (DCs), called functional DCs has been proposed for multilevellogic synthesis. The conventional two-level cubes are generalized to multilevel cubes.Then functional DCs are generated based on the properties of containment. The conceptof containment is more general than unateness which leads to the generation of newDCs. A separate C program has been developed to utilize the functional DCs generatedas a Boolean function is decomposed for both single output and multiple output functions.The program can produce better results than script.rugged of SIS, developed by UC Berkeley,both in area and speed in less CPU time for a number of testcases from MCNC andIWLS'93 benchmarks.In certain applications ANDjXOR (Reed-Muller) logic has shown some attractive advantagesover the standard Boolean logic based on AND JOR operations. A bidirectionalconversion algorithm between these two paradigms is presented based on the concept of polarityfor sum-of-products (SOP) Boolean functions, multiple segment and multiple pointerfacilities. Experimental results show that the algorithm is much faster than the previouslypublished programs for any fixed polarity. Based on this algorithm, a new technique calledredundancy-removal is applied to generalize the idea to very large multiple output Booleanfunctions. Results for benchmarks with up to 199 inputs and 99 outputs are presented.Applying the preceding conversion program, any Boolean functions can be expressedby fixed polarity Reed-Muller forms. There are 2n polarities for an n-variable function andthe number of product terms depends on these polarities. The problem of exact polarityminimization is computationally extensive and current programs are only suitable whenn :::; 15. Based on the comparison of the concepts of polarity in the standard Boolean logicand Reed-Muller logic, a fast algorithm is developed and implemented in C language whichcan find the best polarity for multiple output functions. Benchmark examples of up to 25inputs and 29 outputs run on a personal computer are given.After the best polarity for a Boolean function is calculated, this function can be furthersimplified using mixed polarity methods by combining the adjacent product terms. Hence,an efficient program is developed based on decomposition strategy to implement mixedpolarity minimization for both single output and very large multiple output Boolean functions.Experimental results show that the numbers of product terms are much less thanthe results produced by ESPRESSO for some categories of functions

Synthesis of communicating decentralized supervisors for discrete-event systems with application to communication protocol synthesis

A Discrete-Event Systems (DES) may be viewed as a dynamic system with a discrete state space and a discrete state-transition structure with an event-driven nature, which makes it different from the systems described by differential or difference equations. Given the desired behavior of a DES as a specification, decentralized supervisory control theory seeks to design for a (distributed) DES, consisting of a number of (geographically distant) sites, a set of supervisors, one for each site, such that the behavior of the DES always remains within the specification. If the specification is not coobservable, these supervisors need to communicate amongst each other. This thesis proposes a mathematical framework to formally model and synthesize such communicating decentralized supervisors. The framework provides a decentralized representation of the DES's centralized supervisor and captures its observational and control-related information as mappings, which are called updating and guard functions, respectively. This leads to a polynomial dynamical system, which serves to model the required communication and synthesize its rules. The systematic synthesis, obtained through this approach, characterizes the class of distributed control problems which are solvable only with communication, comes up with a finer partition of it, and addresses practical issues. The thesis ends with the application of the theoretical results to the modeling and synthesis of a communication protoco

A normal accident theory-based complexity assessment methodology for safety-related embedded computer systems

"Computer-related accidents have caused injuries and fatalities in numerous applications. Normal accident theory (NAT) explains that these accidents are inevitable because of system complexity. Complex systems, such as computer-based systems, are highly interconnected, highly interactive, and tightly coupled. We do not have a scientific methodology to identify and quantify these complexities; specifically, NAT has not been operationalized for computer-based systems. Our research addressed this by operationalizing NAT for the system requirements of safety-related computer systems. It was theorized that there are two types of system complexity: external and internal. External complexity was characterized by three variables: system predictability, observability, and usability - the dependent variables. Internal complexity was characterized by modeling system requirements with software cost reduction dependency graphs, then quantifying model attributes using 15 graph-theoretical metrics - the independent variables. Dependent variable data were obtained by having 32 subjects run simulations of our research test vehicle: the light control system (LCS). The LCS simulation tests used a crossover design. Subject perceptions of these simulations were obtained by using a questionnaire. Canonical correlation analysis and structure correlations were used to test hypotheses 1 to 3: the dependent variables predictability, observability, and usability do not correlate with the NAT complexity metrics. Five of fifteen metrics proposed for NAT complexity correlated with the dependent data. These five metrics had structure correlations exceeding 0.25, standard errors <0.10, and a 95% confidence interval. Therefore, the null hypotheses were rejected. A Wilcoxon signed ranks test was used to test hypotheses 4 to 6: increasing NAT complexity increases system predictability, observability, and usability. The results showed that the dependent variables decreased as complexity increased. Therefore, null hypotheses 4 to 6 were rejected. This work is a step forward to operationalize NAT for safety-related computer systems; however, limitations exist. Opportunities addressing these limitations and advancing NAT were identified. Lastly, the major contribution of this work is fundamental to scientific research: to gain knowledge through the discovery of relationship between the variables of interest. Specifically, NAT has been advanced by defining and quantifying complexity measures and showing their inverse relationship to system predictability, observability, and usability." - NIOSHTIC-2NIOSHTIC no. 20024286200

IC spot-defect and fault semantics - a unified framework

A theoretical framework to model spot defects with their related faults in any IC technology is presented. The defect models are unintended geometrical variations introduced in the shape of the patterns of the IC. The transcendence of a defect is determined by the impact that it has at several levels of abstractions. This impact is called a fault. The framework is a mathematical construction which encompasses a hierarchical fault modeling that avoids irrelevant information at every level of abstraction. The framework includes consistency requirements on fault modeling which can be used to analyze the origins and reasons of malfunctions in production chip