Design Methodology for Face Detection Acceleration

A design methodology to accelerate the face detection for embedded systems is described, starting from high level (algorithm optimization) and ending with low level (software and hardware codesign) by addressing the issues and the design decisions made at each level based on the performance measurements and system limitations. The implemented embedded face detection system consumes very little power compared with the traditional PC software implementations while maintaining the same detection accuracy. The proposed face detection acceleration methodology is suitable for real time applications.Ministerio español de Ciencia y Tecnología TEC2011-24319Junta de Andalucía FEDER P08-TIC-0367

FPGA-Based Portable Ultrasound Scanning System with Automatic Kidney Detection

Bedsides diagnosis using portable ultrasound scanning (PUS) offering comfortable diagnosis with various clinical advantages, in general, ultrasound scanners suffer from a poor signal-to-noise ratio, and physicians who operate the device at point-of-care may not be adequately trained to perform high level diagnosis. Such scenarios can be eradicated by incorporating ambient intelligence in PUS. In this paper, we propose an architecture for a PUS system, whose abilities include automated kidney detection in real time. Automated kidney detection is performed by training the Viola–Jones algorithm with a good set of kidney data consisting of diversified shapes and sizes. It is observed that the kidney detection algorithm delivers very good performance in terms of detection accuracy. The proposed PUS with kidney detection algorithm is implemented on a single Xilinx Kintex-7 FPGA, integrated with a Raspberry Pi ARM processor running at 900 MHz

An Adaptive Threshold based FPGA Implementation for Object and Face detection

The moving object and face detection are vital requirement for real time security applications. In this paper, we propose an Adaptive Threshold based FPGA Implementation for Object and Face detection. The input Images and reference Images are preprocessed using Gaussian Filter to smoothen the high frequency components. The 2D-DWT is applied on Gaussian filter outputs and only LL bands are considered for further processing. The modified background with adaptive threshold are used to detect the object with LL band of reference image. The detected object is passed through Gaussian filter to enhance the quality of object. The matching unit is designed to recognize face from standard face database images. It is observed that the performance parameters such as percentage TSR and hardware utilizations are better compared to existing techniques

Face detection hardware accelerator using C-based high-level synthesis

Research has shown that Field Programmable Gate Array (FPGA) based implementation of image processing system results in high computational speed and energy efficiency. However, FPGA design has relatively long development time compared to alternative implementation platforms, such as those based on Central Processing Unit, Graphical Processing Unit or Digital Signal Processor. Designing digital hardware at a higher level of abstraction is an effective way to shorten the development time. High-level synthesis (HLS) raises the abstraction level for designing digital circuit and translates a C-based description of the desired design into Hardware Descriptive Language. However, C-based HLS techniques are still lacking some maturity. In particular, existing works on applying C-based HLS to design hardware that accelerates window-based image processing algorithms are generally done in a trial and error manner, and usually results in non-optimal designs. Hence, there is a need for an effective procedure in applying C-based HLS that can lead to an optimized accelerator design. Therefore, the key contribution of this research is to present a systematic C-based HLS technique to be used in the design of hardware that accelerates image processing algorithm. The proposed C-based HLS design procedure is illustrated with a case study of the Sobel filter. The effectiveness of the proposed design technique is demonstrated by the case study of a Viola- Jones face detection accelerator targeted for implementation in FPGA. The proposed face detection hardware applies a pipelined architecture with task-level parallelism that allows concurrent execution on every sub-module. Experimental results show that the resulting accelerator module achieves a speed performance improvement of up to 12 times when compared to that of existing works. Tested on CMU+MIT database, the proposed accelerator achieves high detection accuracy of 88% and 46 false positives. Experimental results also show that the proposed design achieves up to 61 frames per second detection speed. This work demonstrates that the proposed Cbased HLS design methodology is effective for image processing hardware accelerator development

Energy efficient enabling technologies for semantic video processing on mobile devices

Semantic object-based processing will play an increasingly important role in future multimedia systems due to the ubiquity of digital multimedia capture/playback technologies and increasing storage capacity. Although the object based paradigm has many undeniable benefits, numerous technical challenges remain before the applications becomes pervasive, particularly on computational constrained mobile devices. A fundamental issue is the ill-posed problem of semantic object segmentation. Furthermore, on battery powered mobile computing devices, the additional algorithmic complexity of semantic object based processing compared to conventional video processing is highly undesirable both from a real-time operation and battery life perspective. This thesis attempts to tackle these issues by firstly constraining the solution space and focusing on the human face as a primary semantic concept of use to users of mobile devices. A novel face detection algorithm is proposed, which from the outset was designed to be amenable to be offloaded from the host microprocessor to dedicated hardware, thereby providing real-time performance and reducing power consumption. The algorithm uses an Artificial Neural Network (ANN), whose topology and weights are evolved via a genetic algorithm (GA). The computational burden of the ANN evaluation is offloaded to a dedicated hardware accelerator, which is capable of processing any evolved network topology. Efficient arithmetic circuitry, which leverages modified Booth recoding, column compressors and carry save adders, is adopted throughout the design. To tackle the increased computational costs associated with object tracking or object based shape encoding, a novel energy efficient binary motion estimation architecture is proposed. Energy is reduced in the proposed motion estimation architecture by minimising the redundant operations inherent in the binary data. Both architectures are shown to compare favourable with the relevant prior art

Efficient FPGA implementation and power modelling of image and signal processing IP cores

This thesis was submitted for the degree of Doctor of Philosophy and awarded by Brunel University.Field Programmable Gate Arrays (FPGAs) are the technology of choice in a number ofimage and signal processing application areas such as consumer electronics, instrumentation, medical data processing and avionics due to their reasonable energy consumption, high performance, security, low design-turnaround time and reconfigurability. Low power FPGA devices are also emerging as competitive solutions for mobile and thermally constrained platforms. Most computationally intensive image and signal processing algorithms also consume a lot of power leading to a number of issues including reduced mobility, reliability concerns and increased design cost among others. Power dissipation has become one of the most important challenges, particularly for FPGAs. Addressing this problem requires optimisation and awareness at all levels in the design flow. The key achievements of the work presented in this thesis are summarised here. Behavioural level optimisation strategies have been used for implementing matrix product and inner product through the use of mathematical techniques such as Distributed Arithmetic (DA) and its variations including offset binary coding, sparse factorisation and novel vector level transformations. Applications to test the impact of these algorithmic and arithmetic transformations include the fast Hadamard/Walsh transforms and Gaussian mixture models. Complete design space exploration has been performed on these cores, and where appropriate, they have been shown to clearly outperform comparable existing implementations. At the architectural level, strategies such as parallelism, pipelining and systolisation have been successfully applied for the design and optimisation of a number of cores including colour space conversion, finite Radon transform, finite ridgelet transform and circular convolution. A pioneering study into the influence of supply voltage scaling for FPGA based designs, used in conjunction with performance enhancing strategies such as parallelism and pipelining has been performed. Initial results are very promising and indicated significant potential for future research in this area. A key contribution of this work includes the development of a novel high level power macromodelling technique for design space exploration and characterisation of custom IP cores for FPGAs, called Functional Level Power Analysis and Modelling (FLPAM). FLPAM is scalable, platform independent and compares favourably with existing approaches. A hybrid, top-down design flow paradigm integrating FLPAM with commercially available design tools for systematic optimisation of IP cores has also been developed

Presenter Tracking for Video Recording on Intel Galileo Board.

This paper proposes an intelligent video recording system based on Intel Galileo Gen2 board. The system is able to perform image processing; more precisely face detection and detect a presenter face using OpenCV libraries. Face detection was used to track the presenter’s position with the goal to effectively and autonomously make video recording. Processing images usually require a computer with a higher processing capability. But its application on smaller scale microcontroller can play an important role in the fields of science and technology with application in areas such as in television, video surveillance systems, robotics and industrial inspection. This project successfully integrated a C++ based face detection code with an Arduino sketch for servo motor control on Intel Galileo Gen2. Face detection is achieved by capturing images extract and process single frame to detect face. The Arduino sketch is used to track the detected face by steady control of servo motors to which Logitech C270 720p 3-MP Widescreen HD Webcam is attached. The two processes inter-communicate using a shared memory

Acceleration of real-time face recognition pipeline on heterogeneous hardware platforms

In recent years, advancements in machine learning techniques, and specifically, deep learning methods, have started to create a great impact in the world. With the advent of deep neural network, we are able to achieve unprecedented results in previously unsolvable computer vision tasks. Face recognition, one of the critical computer vision tasks, also sees breakthrough in terms of accuracy. This thesis presents an accelerated and optimized end-to-end face recognition pipeline. Such a pipeline consists of three stages: face detection, alignment, and face recognition/verification. Algorithms for these jobs are extremely computation intensive and thus real-time application was not attainable. In order to bring about the goal of high definition real-time multi-face recognition, we leverage different types of hardware to accelerate detection and recognition stages, which are the most time-consuming stages of the recognition pipeline. To achieve this goal, we leverage an embedded Graphic Processing Unit (GPU) platform as the front end, to perform video capture and face detection. For the back end, we employ a powerful Field-Programming Gate Arrays (FPGA) equipped server, which runs a state-of-the-art deep neural network to recognize faces streamed from the front end with low latency. With the two acceleration schemes targeting GPUs and FPGAs, respectively, we are able to achieve real-time performance for the overall task, and such face recognition system can be widely adopted for various applications