Statistical Classification Based Modelling and Estimation of Analog Circuits Failure Probability

At nanoscales, variations in transistor parameters cause variations and unpredictability in the circuit output, and may ultimately cause a violation of the desired specifications, leading to circuit failure. The parametric variations in transistors occur due to limitations in the manufacturing process and are commonly known as process variations. Circuit simulation is a Computer-Aided Design (CAD) technique for verifying the behavior of analog circuits but exhibits incompleteness under the effects of process variations. Hence, statistical circuit simulation is showing increasing importance for circuit design to address this incompleteness problem. However, existing statistical circuit simulation approaches either fail to analyze the rare failure events accurately and efficiently or are impractical to use. Moreover, none of the existing approaches is able to successfully analyze analog circuits in the presence of multiple performance specifications in timely and accurate manner. Therefore, we propose a new statistical circuit simulation based methodology for modelling and estimation of failure probability of analog circuits in the presence of multiple performance metrics. Our methodology is based on an iterative way of estimating failure probability, employing a statistical classifier to reduce the number of simulations while still maintaining high estimation accuracy. Furthermore, a more practical classifier model is proposed for analog circuit failure probability estimation. Our methodology estimates an accurate failure probability even when the failures resulting from each performance metric occur simultaneously. The proposed methodology can deliver many orders of speedup compared to traditional Monte Carlo methods. Moreover, experimental results show that the methodology generates accurate results for problems with multiple specifications, while other approaches fail totally

Die Monte-Carlo-Simulation in der Unternehmensbewertung : eine financial-modeling-basierte Fallstudie

Die Automobilindustrie befindet sich in einem fundamentalen Wandel. Gesetzgeber drängen den Herstellern von Fahrzeugen aufgrund des Klimawandels vermehrt Vorlagen auf. Diese zwingen die Hersteller wiederum, Fahrzeuge mit weniger oder gar keinen CO2- Emissionen zu produzieren. Ausserdem ist eine vermehrte Ökosensibilität der Konsumierenden zu beobachten. Diese führt zu einem anderen Konsumverhalten und einer Verlagerung der Märkte von Fahrzeugen, die mit fossilen Brennstoffen betrieben werden, zu Fahrzeugen, welche kein CO2 emittieren. Auch die globale Wirtschaftslage und die Inflation tragen zu der künftigen Unsicherheit bei. Dies wirft die Frage auf, wie ein Unternehmen in der Automobilindustrie bewertet werden kann. Eine deterministische Unternehmensbewertung wird diesem Umfeld nicht gerecht. Durch die Erweiterung des deterministischen Modells mit einer MCS kann die Unsicherheit in das Modell miteinbezogen werden. Für die Bewertung wurde der Volkswagen-Konzern gewählt, da dieser einer der weltweit grössten Hersteller von Automobilen ist. Um den Volkswagen-Konzern zu bewerten, wurde in einem ersten Schritt anhand einer PESTEL-Analyse («Political», «Environmental», «Economic», «Social», «Technological» und «Legal») und einer SWOT-Analyse («Strengths», «Weaknesses», «Opportunities» und «Threats») das Umfeld des Volkswagen-Konzerns sowie der Konzern selbst analysiert. In einem zweiten Schritt wurden die Daten für die Annahmen aufbereitet. Diese wurden dann durch die Kombination der Auswertungen der historischen Daten sowie Prognosen anderer Quellen und der PESTEL- sowie der SOWT-Analyse hergeleitet. Im Anschluss wurde mit einer Discounted-Cashflow- Berechnung eine deterministische Bewertung des Volkswagen-Konzerns gemacht. Dieses Modell wurde um die Monte-Carlo-Simulation erweitert, um die Unsicherheit miteinzubeziehen. Die Ergebnisse deuten auf eine starke Unterbewertung des Volkswagen-Konzerns hin. Die in der deterministischen Bewertung ermittelte Marktkapitalisierung von € 162'745 Mio. ist höher als diejenige zum 31.12.2021 mit € 112'848 Mio. und die Marktkapitalisierung von € 98'274 Mio. zum 31.03.2022. Die durch die Monte-Carlo- Simulation ermittelten Werte deuten darauf hin, dass der Wert des Volkswagen-Konzerns die Marktkapitalisierung am 31.12.2021 mit einer Wahrscheinlichkeit von 93.8% übersteigt und diejenige am 31.03.2022 mit einer Wahrscheinlichkeit von 95.3%. Die Monte-Carlo-Simulation kann eine deterministische Bewertung mit mehr Informationen bereichern und bezieht die Unsicherheit mit in die Bewertung ein. Sie ist jedoch kein Allheilmittel, welche die Zukunft zu prognostizieren vermag. Die Subjektivität ist ein zentraler Bestandteil der Bewertung. Auch wenn die Annahmen auf soliden statistischen Analysen und Logik basieren, sind Annahmen ultimativ eine Entscheidung, welche zu einem Zeitpunkt von einer Person aufgrund eines persönlichen Glaubens gefasst wurde. Ausserdem macht die Gewichtung des TV einen Grossteil des Wertes aus und die Ressourcen sollten entsprechend alloziert werden. Aus den Ergebnissen kann auch geschlossen werden, dass Märkte möglicherweise nicht effizient sind und von Emotion sowie Momentum getrieben sein können

Learning Approaches to Analog and Mixed Signal Verification and Analysis

The increased integration and interaction of analog and digital components within a system has amplified the need for a fast, automated, combined analog, and digital verification methodology. There are many automated characterization, test, and verification methods used in practice for digital circuits, but analog and mixed signal circuits suffer from long simulation times brought on by transistor-level analysis. Due to the substantial amount of simulations required to properly characterize and verify an analog circuit, many undetected issues manifest themselves in the manufactured chips. Creating behavioral models, a circuit abstraction of analog components assists in reducing simulation time which allows for faster exploration of the design space. Traditionally, creating behavioral models for non-linear circuits is a manual process which relies heavily on design knowledge for proper parameter extraction and circuit abstraction. Manual modeling requires a high level of circuit knowledge and often fails to capture critical effects stemming from block interactions and second order device effects. For this reason, it is of interest to extract the models directly from the SPICE level descriptions so that these effects and interactions can be properly captured. As the devices are scaled, process variations have a more profound effect on the circuit behaviors and performances. Creating behavior models from the SPICE level descriptions, which include input parameters and a large process variation space, is a non-trivial task. In this dissertation, we focus on addressing various problems related to the design automation of analog and mixed signal circuits. Analog circuits are typically highly specialized and fined tuned to fit the desired specifications for any given system reducing the reusability of circuits from design to design. This hinders the advancement of automating various aspects of analog design, test, and layout. At the core of many automation techniques, simulations, or data collection are required. Unfortunately, for some complex analog circuits, a single simulation may take many days. This prohibits performing any type of behavior characterization or verification of the circuit. This leads us to the first fundamental problem with the automation of analog devices. How can we reduce the simulation cost while maintaining the robustness of transistor level simulations? As analog circuits can vary vastly from one design to the next and are hardly ever comprised of standard library based building blocks, the second fundamental question is how to create automated processes that are general enough to be applied to all or most circuit types? Finally, what circuit characteristics can we utilize to enhance the automation procedures? The objective of this dissertation is to explore these questions and provide suitable evidence that they can be answered. We begin by exploring machine learning techniques to model the design space using minimal simulation effort. Circuit partitioning is employed to reduce the complexity of the machine learning algorithms. Using the same partitioning algorithm we further explore the behavior characterization of analog circuits undergoing process variation. The circuit partitioning is general enough to be used by any CMOS based analog circuit. The ideas and learning gained from behavioral modeling during behavior characterization are used to improve the simulation through event propagation, input space search, complexity and information measurements. The reduction of the input space and behavioral modeling of low complexity, low information primitive elements reduces the simulation time of large analog and mixed signal circuits by 50-75%. The method is extended and applied to assist in analyzing analog circuit layout. All of the proposed methods are implemented on analog circuits ranging from small benchmark circuits to large, highly complex and specialized circuits. The proposed dependency based partitioning of large analog circuits in the time domain allows for fast identification of highly sensitive transistors as well as provides a natural division of circuit components. Modeling analog circuits in the time domain with this partitioning technique and SVM learning algorithms allows for very fast transient behavior predictions, three orders of magnitude faster than traditional simulators, while maintaining 95% accuracy. Analog verification can be explored through a reduction of simulation time by utilizing the partitions, information and complexity measures, and input space reduction. Behavioral models are created using supervised learning techniques for detected primitive elements. We will show the effectiveness of the method on four analog circuits where the simulation time is decreased by 55-75%. Utilizing the reduced simulation method, critical nodes can be found quickly and efficiently. The nodes found using this method match those found by an experienced layout engineer, but are detected automatically given the design and input specifications. The technique is further extended to find the tolerance of transistors to both process variation and power supply fluctuation. This information allows for corrections in layout overdesign or guidance in placing noise reducing components such as guard rings or decoupling capacitors. The proposed approaches significantly reduce the simulation time required to perform the tasks traditionally, maintain high accuracy, and can be automated

기계학습 시스템 설계를 위한 방법

학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2016. 2. 최기영.Machine learning has been paid attention because intelligence such as recognition, decision making, and recommendation is a helpful utility in industrial, medical, transportation, entertainment systems, and others that human need to interact with. As machine learning techniques are extensively applied to various areas, the needs for more robust algorithms and more efficient hardware have been increased. In order to develop an efficient machine learning system, we have researched from high-level algorithm down to low-level hardware logicthe main focus of our work is on ensemble machine learning and stochastic computing (SC). The first work is to combine multiple components, i.e., multiple feature extractors (FE) and multiple classifiers in the aspect of pattern recognition. Ensemble of multiple components is one of challenging approaches for constructing a more accurate classifier. It can handle difficult problems where a single classifier easily makes a wrong decision due to lack of training or parameter optimization. Combining the decisions of participating classifiers statistically reduces the risk of wrong decision. We suggest a hierarchical ensemble framework of multiple feature extractors and multiple classifiers (MFMC). The second work is to construct efficient hardware building blocks for machine learning in order to reduce system complexity and generate high area- and energy-efficient logic, where we exploit the property of machine learning systems that does not require accurate computations. We select stochastic computing (SC), which is an alternative paradigm to conventional binary arithmetic computing. SC can boost efficiency in terms of area, power, and error tolerance, while relaxing the accuracy of computation. The third work is to combine both machine learning and stochastic computing, where we select deep learning. This work presents an efficient DNN design with stochastic computing. Observing that directly adopting stochastic computing to DNN has some challenges including random error fluctuation, range limitation, and overhead in accumulation, we address these problems by removing near-zero weights, applying weight-scaling, and integrating the activation function with the accumulator. The approach allows an easy implementation of early decision termination with a fixed hardware design by exploiting the progressive precision characteristics of stochastic computing, which was not easy with existing approaches. Experimental results show that our approach outperforms the conventional binary logic in terms of gate area, latency, and power consumption.1. Introduction 1 1.1 Hierarchical Ensemble Learning Framework 1 1.2 Hardware Building Block for Machine Learning By Using Stochastic Computing 1 1.2.1 Dynamic energy-accuracy trade-off using stochastic computing in deep neural networks 5 2. A Design Framework for Hierarchical Ensemble of Multiple Feature Extractors and Multiple Classifiers 7 2.1 Introduction 7 2.2 Related work 9 2.3 Proposed hierarchical ensemble system 12 2.3.1 Local Mapping Block and Global Mapping Block 12 2.3.2 Complexity comparison according to composition of LMB 15 2.3.3 Motivation for differentiating local and global mappings17 2.3.4 Reinforcement learning for LMB 19 2.3.5 Construction of Bayesian network from GMB 24 2.4 Experimental results 32 2.4.1 Measure of effectiveness for WMV and RL 33 2.4.2 Pedestrian detection dataset 35 2.4.3 Comparison between GMB and AdaBoost 41 2.4.4 UCI Multiple Features dataset 42 2.4.5 LMB selection 44 2.4.6 Discussion 45 2.5 Conclusion 46 3. Synthesis of Efficient Stochastic Logic for Many-Variable Expressions 49 3.1 Introduction 49 3.2 Related Work 52 3.3 SC Logic Synthesis for Multivariate Expressions 54 3.3.1 Probabilistic Logic 55 3.3.2 Definitions 58 3.3.3 Overview of the Proposed Method 60 3.3.4 Direct Synthesis VS. Kernel-based Synthesis 60 3.3.5 SC Kernel 63 3.3.6 Prime SC Kernel 65 3.3.7 iSC Kernel 68 3.3.8 Relationship Between iSC Kernels 70 3.3.9 Hybrid Scheme 75 3.3.10 Cost Function 76 3.3.11 SC Synthesis Algorithm 78 3.4 Experimental Results 82 3.4.1 Performance of SC Logic Synthesis Algorithm 83 3.4.2 Quality of Synthesis Results 84 3.4.3 Comparison of Accuracy 89 3.5 Conclusion 90 4. An Energy-Efficient Random Number Generator for Stochastic Circuits 91 4.1 Introduction 91 4.2 II. Background 92 4.2.1 Preliminaries 92 4.2.2 Shortcomings of Conventional Approaches 93 4.3 III. Proposed Stochastic Number Generator 96 4.3.1 Overview of the Proposed SNG 96 4.3.2 Even-distribution Encoding 96 4.3.3 Inter-group Randomization 98 4.3.4 Proposed Building Block for Bit Shuffling 100 4.3.5 Intra-group Randomization 102 4.4 Experimental Results 103 4.4.1 Accuracy of Generated Stochastic Bit Stream 104 4.4.2 Area, Delay, Power, Energy and SCC Average 104 4.4.3 Energy Efficiency When Operated under Maximal Precision 105 4.5 Conclusion 106 5. Approximate De-randomizer for Stochastic Circuits 107 5.1 Introduction 107 5.2 Proposed Approximate Parallel Counter 108 5.2.1 Analysis for Gate Count in 1-layer Approximate PC 109 5.2.2 Analysis for Error in 1-layer Approximate PC 110 5.3 Experimental Results 111 5.4 Conclusion 112 6. Dynamic Energy-Accuracy Trade-off Using Stochastic Computing in Deep Neural Networks 113 6.1 Introduction 113 6.2 Background 115 6.4 DNN Using Stochastic Circuit 117 6.4.1 Overview of the Proposed DNN using SC 117 6.4.2 Removing Near-Zero Weights 119 6.4.3 Applying Weight Scaling 120 6.4.4 Activation Function with Accumulation 121 6.5 Early Decision Termination 125 6.5.1 Moving Average Tracking Output Trends 126 6.6 Experimental Results 127 6.6.1 Accuracy of DNN Using SC 128 6.6.2 Effectiveness of Early Decision Termination 129 6.6.3 Comparison of Synthesis Results 130 6.7 Conclusion 132 7. Conclusion 134 Bibliography 136 요약(국문초록) 144Docto