A three-stage ATM switch with cell-level path allocation

A method is described for performing routing in three-stage asynchronous transfer mode (ATM) switches which feature multiple channels between the switch modules in adjacent stages. The method is suited to hardware implementation using parallelism to achieve a very short execution time. This allows cell-level routing to be performed, whereby routes are updated in each time slot. The algorithm allows a contention-free routing to be performed, so that buffering is not required in the intermediate stage. An algorithm with this property, which preserves the cell sequence, is referred to as a path allocation algorithm. A detailed description of the necessary hardware is presented. This hardware uses a novel circuit to count the number of cells requesting each output module, it allocates a path through the intermediate stage of the switch to each cell, and it generates a routing tag for each cell, indicating the path assigned to it. The method of routing tag assignment described employs a nonblocking copy network. The use of highly parallel hardware reduces the clock rate required of the circuitry, for a given-switch size. The performance of ATM switches using this path allocation algorithm has been evaluated by simulation, and is described

MUST, a multicast synchronous transfer application for fast intra-campus replications

In this paper, we introduce a new multicast application called MUST (multicast synchronous transfer) that allows the replication of hard disk partitions in a fast and efficient way. The main goal of MUST is to help system administrators to easily maintain and update all computers in a lab. MUST transmits its IP packets in multicast mode, avoiding the use of unnecessary bandwidth. Unfortunately, the well known TCP transport protocol cannot be used in this multicast environment since the number of TCP flow control windows (and consequently, the number of ACK) that server should process, grow exponentially. Therefore, we also outline an alternative. multicast transport protocol specifically designed for this application. This way, the number of acknowledge frames are drastically reduced, allowing the use of MUST application in a LAN and intra-campus (directly interconnected LANs via few routers). scenarios. The application has been programmed in C language using standard kernel routines, therefore, MUST can mount almost all existing file systems. In addition, we can distribute our application world wide without incurring legal conflicts.This work has been supported by the Spanish Research Council under projects FARIP (TIC2000- 1734-C03-03) and MTCES (TIC2001-3339-C02-02)

Achieving 100% throughput for multicast traffic in input-queued switches

A general approach of designing input-queued multicast switch is to employ multicast switch fabric, where packets can be replicated inside the switch fabric. As compared with unicast switch fabric, the achievable traffic rate region of a switch can be increased, but it is still less than the admissible traffic rate region. In other words, achieving 100% throughput for any admissible multicast traffic pattern is not possible. In this paper, we first revisit the fundamental problems faced by input-queued switch in supporting multicast traffic. We then argue that multicast switch fabric is not necessary if a load-balanced approach is followed. Accordingly, an existing load-balanced two-stage switch architecture [12], consisting of unicast switch fabrics, can be adopted to provide 100% throughput for any admissible multicast traffic pattern. Since the two-stage switch requires no speedup in both switch fabric and packet buffers, we consider it a two-stage input-queued switch. It can be seen that its implementation complexity is much lower than conventional (single-stage) input-queued multicast switches. As compared with the work in [12], our approach is more systematic and we propose a more effective load balancing mechanism. © 2011 IEEE.link_to_subscribed_fulltextProceedings of the IEEE Global Telecommunications Conference (GLOBECOM 2011), Houston, TX, USA, 5-9 December 201

Network Coding in a Multicast Switch

We consider the problem of serving multicast flows in a crossbar switch. We show that linear network coding across packets of a flow can sustain traffic patterns that cannot be served if network coding were not allowed. Thus, network coding leads to a larger rate region in a multicast crossbar switch. We demonstrate a traffic pattern which requires a switch speedup if coding is not allowed, whereas, with coding the speedup requirement is eliminated completely. In addition to throughput benefits, coding simplifies the characterization of the rate region. We give a graph-theoretic characterization of the rate region with fanout splitting and intra-flow coding, in terms of the stable set polytope of the 'enhanced conflict graph' of the traffic pattern. Such a formulation is not known in the case of fanout splitting without coding. We show that computing the offline schedule (i.e. using prior knowledge of the flow arrival rates) can be reduced to certain graph coloring problems. Finally, we propose online algorithms (i.e. using only the current queue occupancy information) for multicast scheduling based on our graph-theoretic formulation. In particular, we show that a maximum weighted stable set algorithm stabilizes the queues for all rates within the rate region.Comment: 9 pages, submitted to IEEE INFOCOM 200

Fault-Tolerant Multicasting in Multistage Interconnection Networks

Abstract In this paper, we study fault-toleran

Multicast cross-path ATM switches: principles, designs and performance evaluations.

by Lin Hon Man.Thesis (M.Phil.)--Chinese University of Hong Kong, 1998.Includes bibliographical references (leaves 59-[63]).Chapter 1 --- Introduction --- p.1Chapter 1.1 --- Organization of Thesis --- p.3Chapter 2 --- Principles of Multicast Cross-Path Switches --- p.4Chapter 2.1 --- Introduction --- p.4Chapter 2.2 --- Unicast Cross-Path switch --- p.5Chapter 2.2.1 --- Routing properties in Clos networks --- p.5Chapter 2.2.2 --- Quasi-static routing procedures --- p.5Chapter 2.2.3 --- Capacity and Route Assignment --- p.7Chapter 2.3 --- Multicast Cross-Path Switch --- p.8Chapter 2.3.1 --- Scheme 1 - Cell replication performed at both input and output stages --- p.10Chapter 2.3.2 --- Scheme 2 - Cell replication performed only at the input stage --- p.10Chapter 3 --- Architectures --- p.14Chapter 3.1 --- Introduction --- p.14Chapter 3.2 --- Input Module Design (Scheme 1) --- p.16Chapter 3.2.1 --- Input Header Translator --- p.16Chapter 3.2.2 --- Input Module Controller --- p.17Chapter 3.2.3 --- Input Replication Network (Scheme 1) --- p.19Chapter 3.2.4 --- Routing Network --- p.23Chapter 3.3 --- Central Modules --- p.24Chapter 3.4 --- Output Module Design (Scheme 1) --- p.24Chapter 3.5 --- Input Module Design (Scheme 2) --- p.25Chapter 3.5.1 --- Input Header Translator (Scheme 2) --- p.26Chapter 3.5.2 --- Input Module Controller (Scheme 2) --- p.27Chapter 3.5.3 --- Input Replication Network (Scheme 2) --- p.28Chapter 3.6 --- Output Module Design (Scheme 2) --- p.29Chapter 4 --- Performance Evaluations --- p.31Chapter 4.1 --- Introduction --- p.31Chapter 4.2 --- Traffic characteristics --- p.31Chapter 4.2.1 --- Fanout distribution --- p.31Chapter 4.2.2 --- Middle stage traffic load and its calculation --- p.32Chapter 4.3 --- Throughput Performance --- p.34Chapter 4.4 --- Delay Performance --- p.37Chapter 4.4.1 --- Input Stage Delay --- p.38Chapter 4.4.2 --- Output Stage Delay --- p.39Chapter 4.5 --- Cell Loss Performance --- p.43Chapter 4.5.1 --- Cell Loss due to Buffer Overflow --- p.44Chapter 4.5.2 --- Cell Loss Due to Output Contention --- p.45Chapter 4.6 --- Complexities --- p.50Chapter 5 --- Conclusions --- p.57Bibliography --- p.5

Concentrators in ATM switching.

by Lau Chu Man.Thesis (M.Phil.)--Chinese University of Hong Kong, 1995.Includes bibliographical references (leaves 76-83).Chapter 1 --- Introduction --- p.1Chapter 2 --- Basic Notions --- p.13Chapter 3 --- Fast Knockout --- p.19Chapter 3.1 --- The Algorithm of Fast Knockout --- p.20Chapter 3.2 --- Complexity of the Fast Knockout Algorithm --- p.29Chapter 3.3 --- Summary --- p.35Chapter 4 --- k-Sortout --- p.36Chapter 4.1 --- A Brief Review of k-Sorting --- p.37Chapter 4.2 --- The Algorithm of k-Sortout --- p.47Chapter 4.3 --- Complexity of the k- Sortout Algorithm --- p.53Chapter 4.4 --- Summary --- p.58Chapter 5 --- General Sortout --- p.59Chapter 5.1 --- The General Algorithm of Sortout --- p.59Chapter 5.2 --- Complexity of Concentrators by the General Algorithm --- p.64Chapter 5.3 --- Summary --- p.69Chapter 6 --- Concluding Remarks --- p.70Chapter 6.1 --- Summary of Results --- p.70Chapter 6.2 --- Directions for Further Research --- p.73Bibliography --- p.7

Design and analysis of a scalable terabit multicast packet switch : architecture and scheduling algorithms

Internet growth and success not only open a primary route of information exchange for millions of people around the world, but also create unprecedented demand for core network capacity. Existing switches/routers, due to the bottleneck from either switch architecture or arbitration complexity, can reach a capacity on the order of gigabits per second, but few of them are scalable to large capacity of terabits per second. In this dissertation, we propose three novel switch architectures with cooperated scheduling algorithms to design a terabit backbone switch/router which is able to deliver large capacity, multicasting, and high performance along with Quality of Service (QoS). Our switch designs benefit from unique features of modular switch architecture and distributed resource allocation scheme. Switch I is a unique and modular design characterized by input and output link sharing. Link sharing resolves output contention and eliminates speedup requirement for central switch fabric. Hence, the switch architecture is scalable to any large size. We propose a distributed round robin (RR) scheduling algorithm which provides fairness and has very low arbitration complexity. Switch I can achieve good performance under uniform traffic. However, Switch I does not perform well for non-uniform traffic. Switch II, as a modified switch design, employs link sharing as well as a token ring to pursue a solution to overcome the drawback of Switch 1. We propose a round robin prioritized link reservation (RR+POLR) algorithm which results in an improved performance especially under non-uniform traffic. However, RR+POLR algorithm is not flexible enough to adapt to the input traffic. In Switch II, the link reservation rate has a great impact on switch performance. Finally, Switch III is proposed as an enhanced switch design using link sharing and dual round robin rings. Packet forwarding is based on link reservation. We propose a queue occupancy based dynamic link reservation (QOBDLR) algorithm which can adapt to the input traffic to provide a fast and fair link resource allocation. QOBDLR algorithm is a distributed resource allocation scheme in the sense that dynamic link reservation is carried out according to local available information. Arbitration complexity is very low. Compared to the output queued (OQ) switch which is known to offer the best performance under any traffic pattern, Switch III not only achieves performance as good as the OQ switch, but also overcomes speedup problem which seriously limits the OQ switch to be a scalable switch design. Hence, Switch III would be a good choice for high performance, scalable, large-capacity core switches

Performance study of multirate circuit switching in quantized clos network.

by Vincent Wing-Shing Tse.Thesis submitted in: December 1997.Thesis (M.Phil.)--Chinese University of Hong Kong, 1998.Includes bibliographical references (leaves 62-[64]).Abstract also in Chinese.Chapter 1 --- Introduction --- p.1Chapter 2 --- Principles of Multirate Circuit Switching in Quantized Clos Network --- p.10Chapter 2.1 --- Formulation of Multirate Circuit Switching --- p.11Chapter 2.2 --- Call Level Routing in Quantized Clos Network --- p.12Chapter 2.3 --- Cell Level Routing in Quantized Clos Network --- p.16Chapter 2.3.1 --- Traffic Behavior in ATM Network --- p.17Chapter 2.3.2 --- Time Division Multiplexing in Multirate Circuit Switching and Cell-level Switching in ATM Network --- p.19Chapter 2.3.3 --- Cell Transmission Scheduling --- p.20Chapter 2.3.4 --- Capacity Allocation and Route Assignment at Cell-level --- p.29Chapter 3 --- Performance Evaluation of Different Implementation Schemes --- p.31Chapter 3.1 --- Global Control and Distributed Switching --- p.32Chapter 3.2 --- Implementation Schemes of Quantized Clos Network --- p.33Chapter 3.2.1 --- Classification of Switch Modules --- p.33Chapter 3.2.2 --- Bufferless Switch Modules Construction Scheme --- p.38Chapter 3.2.3 --- Buffered Switch Modules Construction Scheme --- p.42Chapter 3.3 --- Complexity Comparison --- p.44Chapter 3.4 --- Delay Performance of The Two Implementation Schemes --- p.47Chapter 3.4.1 --- Assumption --- p.47Chapter 3.4.2 --- Simulation Result --- p.50Chapter 4 --- Conclusions --- p.59Bibliography --- p.6