Delay-Based Controller Design for Continuous-Time and Hybrid Applications

Motivated by the availability of different types of delays in embedded systems and biological circuits, the objective of this work is to study the benefits that delay can provide in simplifying the implementation of controllers for continuous-time systems. Given a continuous-time linear time-invariant (LTI) controller, we propose three methods to approximate this controller arbitrarily precisely by a simple controller composed of delay blocks, a few integrators and possibly a unity feedback. Different problems associated with the approximation procedures, such as finding the optimal number of delay blocks or studying the robustness of the designed controller with respect to delay values, are then investigated. We also study the design of an LTI continuous-time controller satisfying given control objectives whose delay-based implementation needs the least number of delay blocks. A direct application of this work is in the sampled-data control of a real-time embedded system, where the sampling frequency is relatively high and/or the output of the system is sampled irregularly. Based on our results on delay-based controller design, we propose a digital-control scheme that can implement every continuous-time stabilizing (LTI) controller. Unlike a typical sampled-data controller, the hybrid controller introduced here -— consisting of an ideal sampler, a digital controller, a number of modified second-order holds and possibly a unity feedback -— is robust to sampling jitter and can operate at arbitrarily high sampling frequencies without requiring expensive, high-precision computation

Regression modeling for digital test of ΣΔ modulators

The cost of Analogue and Mixed-Signal circuit testing is an important bottleneck in the industry, due to timeconsuming verification of specifications that require state-ofthe- art Automatic Test Equipment. In this paper, we apply the concept of Alternate Test to achieve digital testing of converters. By training an ensemble of regression models that maps simple digital defect-oriented signatures onto Signal to Noise and Distortion Ratio (SNDR), an average error of 1:7% is achieved. Beyond the inference of functional metrics, we show that the approach can provide interesting diagnosis information.Ministerio de Educación y Ciencia TEC2007-68072/MICJunta de Andalucía TIC 5386, CT 30

Noise-Sensitive Loops Identification for Linear Time-Varying Analog Circuits

The continuing scaling of VLSI technology and the increase of design complexity have rendered the robustness of analog circuits a significant design concern. Analog circuits with strong parasitic effects can be modeled using a multi-loop structure, which is more sophisticated than the traditional single feedback loop structure and results in a more complex small signal stability analysis from the noise perspective. A Loop Finder algorithm has been proposed to allow designers to detect and identify noise-sensitive return loops, which are also called "unstable" loops in previous works, without the need to add breakpoints in the circuit. Besides, efficient pole discovery and impedance computation methods have been explored so that the Loop Finder algorithm can deal with very large scale analog circuits in a reasonable amount of time. However, this algorithm only works for circuits that can be described using a linear time-invariant (LTI) system model. Many practical circuits, such as switch capacitor filters, mixers and so on, have time-varying behaviors. To describe such circuits, a linear time-varying (LTV) system model needs to be employed. In this research, we first examine the stability property of LTV systems in time domain, mostly based upon the Floquet Theory. We then take an in-depth look at the transfer function of an LTV system in the frequency domain and build the link between it and the Floquet theory. Finally, we propose an efficient algorithm for identifying noise-sensitive loops in linear time-varying circuits. This methodology provides a unifying solution for loop-based noise analysis for both LTI and LTV circuits

System Identification, Diagnosis, and Built-In Self-Test of High Switching Frequency DC-DC Converters

abstract: Complex electronic systems include multiple power domains and drastically varying dynamic power consumption patterns, requiring the use of multiple power conversion and regulation units. High frequency switching converters have been gaining prominence in the DC-DC converter market due to smaller solution size (higher power density) and higher efficiency. As the filter components become smaller in value and size, they are unfortunately also subject to higher process variations and worse degradation profiles jeopardizing stable operation of the power supply. This dissertation presents techniques to track changes in the dynamic loop characteristics of the DC-DC converters without disturbing the normal mode of operation. A digital pseudo-noise (PN) based stimulus is used to excite the DC-DC system at various circuit nodes to calculate the corresponding closed-loop impulse response. The test signal energy is spread over a wide bandwidth and the signal analysis is achieved by correlating the PN input sequence with the disturbed output generated, thereby accumulating the desired behavior over time. A mixed-signal cross-correlation circuit is used to derive on-chip impulse responses, with smaller memory and lower computational requirement in comparison to a digital correlator approach. Model reference based parametric and non-parametric techniques are discussed to analyze the impulse response results in both time and frequency domain. The proposed techniques can extract open-loop phase margin and closed-loop unity-gain frequency within 5.2% and 4.1% error, respectively, for the load current range of 30-200mA. Converter parameters such as natural frequency (ω_n ), quality factor (Q), and center frequency (ω_c ) can be estimated within 3.6%, 4.7%, and 3.8% error respectively, over load inductance of 4.7-10.3µH, and filter capacitance of 200-400nF. A 5-MHz switching frequency, 5-8.125V input voltage range, voltage-mode controlled DC-DC buck converter is designed for the proposed built-in self-test (BIST) analysis. The converter output voltage range is 3.3-5V and the supported maximum load current is 450mA. The peak efficiency of the converter is 87.93%. The proposed converter is fabricated on a 0.6µm 6-layer-metal Silicon-On-Insulator (SOI) technology with a die area of 9mm^2 . The area impact due to the system identification blocks including related I/O structures is 3.8% and they consume 530µA quiescent current during operation.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201

Low Power Adaptive Circuits: An Adaptive Log Domain Filter and A Low Power Temperature Insensitive Oscillator Applied in Smart Dust Radio

This dissertation focuses on exploring two low power adaptive circuits. One is an adaptive filter at audio frequency for system identification. The other is a temperature insensitive oscillator for low power radio frequency communication. The adaptive filter is presented with integrated learning rules for model reference estimation. The system is a first order low pass filter with two parameters: gain and cut-off frequency. It is implemented using multiple input floating gate transistors to realize online learning of system parameters. Adaptive dynamical system theory is used to derive robust control laws in a system identification task. Simulation results show that convergence is slower using simplified control laws but still occurs within milliseconds. Experimental results confirm that the estimated gain and cut-off frequency track the corresponding parameters of the reference filter. During operation, deterministic errors are introduced by mismatch within the analog circuit implementation. An analysis is presented which attributes the errors to current mirror mismatch. The harmonic distortion of the filter operating in different inversion is analyzed using EKV model numerically. The temperature insensitive oscillator is designed for a low power wireless network. The system is based on a current starved ring oscillator implemented using CMOS transistors instead of LC tank for less chip area and power consumption. The frequency variance with temperature is compensated by the temperature adaptive circuits. Experimental results show that the frequency stability from 5°C to 65°C has been improved 10 times with automatic compensation and at least 1 order less power is consumed than published competitors. This oscillator is applied in a 2.2GHz OOK transmitter and a 2.2GHz phase locked loop based FM receiver. With the increasing needs of compact antenna, possible high data rate and wide unused frequency range of short distance communication, a higher frequency phase locked loop used for BFSK receiver is explored using an LC oscillator for its capability at 20GHz. The success of frequency demodulation is demonstrated in the simulation results that the PLL can lock in 0.5μs with 35MHz lock-in range and 2MHz detection resolution. The model of a phase locked loop used for BFSK receiver is analyzed using Matlab

A review of advances in pixel detectors for experiments with high rate and radiation

The Large Hadron Collider (LHC) experiments ATLAS and CMS have established hybrid pixel detectors as the instrument of choice for particle tracking and vertexing in high rate and radiation environments, as they operate close to the LHC interaction points. With the High Luminosity-LHC upgrade now in sight, for which the tracking detectors will be completely replaced, new generations of pixel detectors are being devised. They have to address enormous challenges in terms of data throughput and radiation levels, ionizing and non-ionizing, that harm the sensing and readout parts of pixel detectors alike. Advances in microelectronics and microprocessing technologies now enable large scale detector designs with unprecedented performance in measurement precision (space and time), radiation hard sensors and readout chips, hybridization techniques, lightweight supports, and fully monolithic approaches to meet these challenges. This paper reviews the world-wide effort on these developments.Comment: 84 pages with 46 figures. Review article.For submission to Rep. Prog. Phy

Triaxial digital fluxgate magnetometer for NASA applications explorer mission: Results of tests of critical elements

Tests performed to prove the critical elements of the triaxial digital fluxgate magnetometer design were described. A method for improving the linearity of the analog to digital converter portion of the instrument was studied in detail. A sawtooth waveform was added to the signal being measured before the A/D conversion, and averaging the digital readings over one cycle of the sawtooth. It was intended to reduce bit error nonlinearities present in the A/D converter which could be expected to be as much as 16 gamma if not reduced. No such nonlinearities were detected in the output of the instrument which included the feature designed to reduce these nonlinearities. However, a small scale nonlinearity of plus or minus 2 gamma with a 64 gamma repetition rate was observed in the unit tested. A design improvement intended to eliminate this small scale nonlinearity was examined

RF applications in digital signal processing

Ever higher demands for stability, accuracy, reproducibility, and monitoring capability are being placed on Low-Level Radio Frequency (LLRF) systems of particle accelerators. Meanwhile, continuing rapid advances in digital signal processing technology are being exploited to meet these demands, thus leading to development of digital LLRF systems. The rst part of this course will begin by focusing on some of the important building-blocks of RF signal processing including mixer theory and down-conversion, I/Q (amplitude and phase) detection, digital down-conversion (DDC) and decimation, concluding with a survey of I/Q modulators. The second part of the course will introduce basic concepts of feedback systems, including examples of digital cavity eld and phase control, followed by radial loop architectures. Adaptive feed-forward systems used for the suppression of repetitive beam disturbances will be examined. Finally, applications and principles of system identi cation approaches will be summarized

34th Midwest Symposium on Circuits and Systems-Final Program

Organized by the Naval Postgraduate School Monterey California. Cosponsored by the IEEE Circuits and Systems Society. Symposium Organizing Committee: General Chairman-Sherif Michael, Technical Program-Roberto Cristi, Publications-Michael Soderstrand, Special Sessions- Charles W. Therrien, Publicity: Jeffrey Burl, Finance: Ralph Hippenstiel, and Local Arrangements: Barbara Cristi