Performance evaluation of the time delay digital tanlock loop architectures

This article presents the architectures, theoretical analyses and testing results of modified time delay digital tanlock loop (TDTLs) system. The modifications to the original TDTL architecture were introduced to overcome some of the limitations of the original TDTL and to enhance the overall performance of the particular systems. The limitations addressed in this article include the non-linearity of the phase detector, the restricted width of the locking range and the overall system acquisition speed. Each of the modified architectures was tested by subjecting the system to sudden positive and negative frequency steps and comparing its response with that of the original TDTL. In addition, the performance of all the architectures was evaluated under noise-free as well as noisy environments. The extensive simulation results using MATLAB/SIMULINK demonstrate that the new architectures overcome the limitations they addressed and the overall results confirmed significant improvements in performance compared to the conventional TDTL system

On Phase Noise Suppression in Full-Duplex Systems

Oscillator phase noise has been shown to be one of the main performance limiting factors in full-duplex systems. In this paper, we consider the problem of self-interference cancellation with phase noise suppression in full-duplex systems. The feasibility of performing phase noise suppression in full-duplex systems in terms of both complexity and achieved gain is analytically and experimentally investigated. First, the effect of phase noise on full-duplex systems and the possibility of performing phase noise suppression are studied. Two different phase noise suppression techniques with a detailed complexity analysis are then proposed. For each suppression technique, both free-running and phase locked loop based oscillators are considered. Due to the fact that full-duplex system performance highly depends on hardware impairments, experimental analysis is essential for reliable results. In this paper, the performance of the proposed techniques is experimentally investigated in a typical indoor environment. The experimental results are shown to confirm the results obtained from numerical simulations on two different experimental research platforms. At the end, the tradeoff between the required complexity and the gain achieved using phase noise suppression is discussed.Comment: Published in IEEE transactions on wireless communications on October-2014. Please refer to the IEEE version for the most updated documen

All-Digital Self-interference Cancellation Technique for Full-duplex Systems

Full-duplex systems are expected to double the spectral efficiency compared to conventional half-duplex systems if the self-interference signal can be significantly mitigated. Digital cancellation is one of the lowest complexity self-interference cancellation techniques in full-duplex systems. However, its mitigation capability is very limited, mainly due to transmitter and receiver circuit's impairments. In this paper, we propose a novel digital self-interference cancellation technique for full-duplex systems. The proposed technique is shown to significantly mitigate the self-interference signal as well as the associated transmitter and receiver impairments. In the proposed technique, an auxiliary receiver chain is used to obtain a digital-domain copy of the transmitted Radio Frequency (RF) self-interference signal. The self-interference copy is then used in the digital-domain to cancel out both the self-interference signal and the associated impairments. Furthermore, to alleviate the receiver phase noise effect, a common oscillator is shared between the auxiliary and ordinary receiver chains. A thorough analytical and numerical analysis for the effect of the transmitter and receiver impairments on the cancellation capability of the proposed technique is presented. Finally, the overall performance is numerically investigated showing that using the proposed technique, the self-interference signal could be mitigated to ~3dB higher than the receiver noise floor, which results in up to 76% rate improvement compared to conventional half-duplex systems at 20dBm transmit power values.Comment: Submitted to IEEE Transactions on Wireless Communication

Sensitivity of Multi Carrier 2 Dimensional Spreading systems to carrier phase noise

5 pagesPhase noise is a topic of theoretical and practical interest in electronic circuits. Although progress has been made in the characterization of its description, there still considerable gaps in its effect especially on the multi carrier spreading systems. In this paper, we investigate the impact of a local oscillator phase noise on the multi carrier 2 dimensional spreading systems known as OFDM-CDMA. The contribution of this paper is twofold. First, we use some properties of random matrix and free probability theory to give a simplified expression of the Signal to Interference and Noise Ratio SINR obtained after equalization and despreading. The latter is independent of the actual value of the spreading codes of different users and depends principally on the complex amplitudes of the estimated channel coefficients. Second, we use this expression to derive new weighting functions which are very interesting for the RF engineers when they design the frequency synthesizer. Simulation results are provided to discuss and validate our model

Phase Noise and Frequency Stability of the Red-Pitaya Internal PLL

partially_open5sìIn field-programmable gate array platforms, the main clock is generally a low-cost quartz oscillator whose stability is of the order of 10-9 to 10-10 in the short term and 10-7 to 10-8 in the medium term, with the uncertainty of tens of ppm. Better stability is achieved by feeding an external reference into the internal phase-locked loop (PLL). We report the noise characterization of the internal PLL of Red-Pitaya platform, an open-source embedded system architected around the Zynq 7010 System on Chip, with analog-to-digital and digital-to-analog converters. Our experiments show that, providing an external 10-MHz reference, the PLL exhibits a residual frequency stability of 1.2×10-12 at 1 s and 1.3×10-15 at 4000 s, Allan deviation in 5-Hz bandwidth. These results help to predict the PLL stability as a function of frequency and power of the external reference, and provide guidelines for the design of precision instrumentation, chiefly intended for time and frequency metrology.partially_openCardenas Olaya, Andrea Carolina; Calosso, Claudio Eligio; Friedt, Jean-Michel; Micalizio, Salvatore; Rubiola, EnricoCardenas Olaya, Andrea Carolina; Calosso, Claudio Eligio; Friedt, Jean-Michel; Micalizio, Salvatore; Rubiola, Enric

Digital tanlock loop architecture with no delay

This article proposes a new architecture for a digital tanlock loop which eliminates the time-delay block. The �=2 (rad) phase shift relationship between the two channels, which is generated by the delay block in the conventional timedelay digital tanlock loop (TDTL), is preserved using two quadrature sampling signals for the loop channels. The proposed system outperformed the original TDTL architecture, when both systems were tested with frequency shift keying input signal. The new system demonstrated better linearity and acquisition speed as well as improved noise performance compared with the original TDTL architecture. Furthermore, the removal of the time-delay block enables all processing to be digitally performed, which reduces the implementation complexity. Both the original TDTL and the new architecture without the delay block were modelled and simulated using ATLAB/Simulink. Implementation issues, including complexity and relation to simulation of both architectures, are also addressed