Analytical Method for Joint Optimization of Ffe and Dfe Equalizations for Multi-Level Signals

Channel equalization is the efficient method for recovering distorted signal and correspondingly reducing bit error rate (BER). Different type of equalizations, like feed forward equalization (FFE) and decision feedback equalization (DFE) are canceling channel effect and recovering channel response. Separate optimization of tap coefficients for FFE and DFE does not give optimal result. In this case FFE and DFE tap coefficients are found separately and they are not collaborating. Therefore, the final equalization result is not global optimal. In the present paper new analytical method for finding best tap coefficients for FFE and DFE joint equalization is introduced. The proposed method can be used for both NRZ and PAM4 signals. The idea of the methodology is to combine FFE and DFE tap coefficients into one optimization problem and allow them to collaborate and lead to the global optimal solution. The proposed joint optimization method is fast, easy to implement and efficient. The method has been tested for several measured channels and the analysis of the results are discussed

Soft-Decision Low-Complexity Chase Decoders for the RS(255,239) Code

[EN] In this work, we present a new architecture for soft-decision Reed-Solomon (RS) Low-Complexity Chase (LCC) decoding. The proposed architecture is scalable and can be used for a high number of test vectors. We propose a novel Multiplicity Assignment stage that sorts and stores only the location of the errors inside the symbols and the powers of a that identify the positions of the symbols in the frame. Novel schematics for the Syndrome Update and Symbol Modification blocks that are adapted to the proposed sorting stage are also presented. We also propose novel solutions for the problems that arise when a high number of test vectors is processed. We implemented three decoders: a h = 4 LCC decoder and two decoders that only decode 31 and 60 test vectors of true h = 5 and h = 6 LCC decoders, respectively. For example, our h = 4 decoder requires 29% less look-up tables in Virtex-V Field Programmable Gate Array (FPGA) devices than the best soft-decision RS decoder published to date, while has a 0.07 dB coding gain over that decoder.This research was funded by the Spanish Ministerio de Economia y Competitividad and FEDER grant number TEC2015-70858-C2-2-RTorres Carot, V.; Valls Coquillat, J.; Canet Subiela, MJ.; García Herrero, FM. (2019). Soft-Decision Low-Complexity Chase Decoders for the RS(255,239) Code. Electronics. 8(1):1-13. https://doi.org/10.3390/electronics8010010S11381Cideciyan, R., Gustlin, M., Li, M., Wang, J., & Wang, Z. (2013). Next generation backplane and copper cable challenges. IEEE Communications Magazine, 51(12), 130-136. doi:10.1109/mcom.2013.6685768Koetter, R., & Vardy, A. (2003). Algebraic soft-decision decoding of reed-solomon codes. IEEE Transactions on Information Theory, 49(11), 2809-2825. doi:10.1109/tit.2003.819332Sudan, M. (1997). Decoding of Reed Solomon Codes beyond the Error-Correction Bound. Journal of Complexity, 13(1), 180-193. doi:10.1006/jcom.1997.0439Guruswami, V., & Sudan, M. (1999). Improved decoding of Reed-Solomon and algebraic-geometry codes. IEEE Transactions on Information Theory, 45(6), 1757-1767. doi:10.1109/18.782097Jiang, J., & Narayanan, K. R. (2008). Algebraic Soft-Decision Decoding of Reed–Solomon Codes Using Bit-Level Soft Information. IEEE Transactions on Information Theory, 54(9), 3907-3928. doi:10.1109/tit.2008.928238Jiangli Zhu, Xinmiao Zhang, & Zhongfeng Wang. (2009). Backward Interpolation Architecture for Algebraic Soft-Decision Reed–Solomon Decoding. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 17(11), 1602-1615. doi:10.1109/tvlsi.2008.2005575Jiangli Zhu, & Xinmiao Zhang. (2008). Efficient VLSI Architecture for Soft-Decision Decoding of Reed–Solomon Codes. IEEE Transactions on Circuits and Systems I: Regular Papers, 55(10), 3050-3062. doi:10.1109/tcsi.2008.923169Zhongfeng Wang, & Jun Ma. (2006). High-Speed Interpolation Architecture for Soft-Decision Decoding of Reed–Solomon Codes. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 14(9), 937-950. doi:10.1109/tvlsi.2006.884046Zhang, X. (2006). Reduced Complexity Interpolation Architecture for Soft-Decision Reed–Solomon Decoding. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 14(10), 1156-1161. doi:10.1109/tvlsi.2006.884177Xinmiao Zhang, & Parhi, K. K. (2005). Fast factorization architecture in soft-decision Reed-Solomon decoding. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 13(4), 413-426. doi:10.1109/tvlsi.2004.842914Bellorado, J., & Kavcic, A. (2010). Low-Complexity Soft-Decoding Algorithms for Reed–Solomon Codes—Part I: An Algebraic Soft-In Hard-Out Chase Decoder. IEEE Transactions on Information Theory, 56(3), 945-959. doi:10.1109/tit.2009.2039073García-Herrero, F., Valls, J., & Meher, P. K. (2011). High-Speed RS(255, 239) Decoder Based on LCC Decoding. Circuits, Systems, and Signal Processing, 30(6), 1643-1669. doi:10.1007/s00034-011-9327-4Zhang, W., Wang, H., & Pan, B. (2013). Reduced-Complexity LCC Reed–Solomon Decoder Based on Unified Syndrome Computation. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 21(5), 974-978. doi:10.1109/tvlsi.2012.2197030Peng, X., Zhang, W., Ji, W., Liang, Z., & Liu, Y. (2015). Reduced-Complexity Multiplicity Assignment Algorithm and Architecture for Low-Complexity Chase Decoder of Reed-Solomon Codes. IEEE Communications Letters, 19(11), 1865-1868. doi:10.1109/lcomm.2015.2477495Lin, Y.-M., Hsu, C.-H., Chang, H.-C., & Lee, C.-Y. (2014). A 2.56 Gb/s Soft RS (255, 239) Decoder Chip for Optical Communication Systems. IEEE Transactions on Circuits and Systems I: Regular Papers, 61(7), 2110-2118. doi:10.1109/tcsi.2014.2298282Wu, Y. (2015). New Scalable Decoder Architectures for Reed–Solomon Codes. IEEE Transactions on Communications, 63(8), 2741-2761. doi:10.1109/tcomm.2015.2445759Garcia-Herrero, F., Canet, M. J., Valls, J., & Meher, P. K. (2012). High-Throughput Interpolator Architecture for Low-Complexity Chase Decoding of RS Codes. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 20(3), 568-573. doi:10.1109/tvlsi.2010.210396

Wireless Channel Modeling For Networks On Chips

The advent of integrated circuit (chip) multiprocessors (CMPs) combined with the continuous reduction in device physical size (technology scaling) to the sub-nanometer regime will result in an exponential increase in the number of processing cores that can be integrated within a single chip. Today’s CMPs already support tens to low hundreds of cores and both industry and academic roadmaps project that future chips will have thousands of cores. Therefore, while there are open questions on how to harness the computing power offered by CMPs, the design of power-efficient and compact on-chip interconnection networks that connects cores, caches and memory controllers has become imperative for sustaining the performance of CMPs. As the limited scalability of bus-based networks degrades performance by reducing data rates and increasing latency, the Network-on-Chip (NoC) design paradigm has gained momentum, where a network of routers and links connects all the cores. However, power consumption of NoCs is a significant challenge that should be addressed to capitalize on the scaling advantages of multicores. Also, improvements in metal wire characteristics will no longer satisfy the power and performance requirements of on-chip communication. One approach to continue the performance improvements is to integrate new emerging technologies into the electronic design flow such as wireless/RF technologies, since they provide unique advantages that make them desirable in a NoC environment. First, wireless technologies are ubiquitous and offer a wide range of options in communication, and there exists a vast body of knowledge for the design and implementation of wireless chipsets using RF-CMOS technology. Second, wireless communication, unlike wired transmission, can be omnidirectional, which can facilitate one-hop unicast, multicast, and broadcast communication that can result in a reduction in power consumption while allowing for faster communication. Third, wireless communication can increase the communication data rate by the combination of Frequency Division Multiplexing (FDM) and Time Division Multiplexing (TDM) (and in the future, potentially spatial division multiplexing (SDM)). Therefore, Wireless NoC (WiNoC) interconnects have recently emerged as a viable solution to mitigate power concerns in the short to medium term while still providing competitive performance metrics, i.e., low power consumption, tens of Gbps data rates, and minimal circuit area (or volume) within the chip. Worth noting is that wireless links are not envisioned as replacing all wired links, but rather as augmenting the wired interconnection network. In this dissertation, we employ simulations in HFSS from Ansys® to present accurate wireless channel models for a realistic WiNoC environment. We investigate the performance of these models with different types of narrowband and wideband antennas. This entails estimation of the scattering parameters for the channels between multiple antenna elements in the WiNoC, from which we derive channel transfer functions and channel impulse responses. Using these results, we can estimate the throughput of the various WiNoC links, and this allows us to design effective multiple access (MA) schemes via FDM and TDM. For these MA schemes, we provide estimates of maximal throughput. To further the feasibility study, we investigate the performance of a simple binary transmission scheme--On-Off Keying (OOK)--through the resulting dispersive channels, which can facilitate one-hop unicast, multicast, and broadcast communication that can result in a reduction in power consumption while allowing for faster communication. Our investigation of the performance of On-Off Keying modulation (OOK) also includes an analytical expression for bit error ratio (BER) that can be evaluated numerically. This enables us to provide the equalization requirements needed to achieve our target BERs. Finally, we provide recommendations for WiNoC design and future tasks related to this research

Advances in local area optical data communication systems

This paper reviews optical fibre technology for local area optical communications systems. Technologies used in local systems include single and multimode fibre, single and multimode lasers, optical modulators, photodetectors, wavelength division multiplexing, multilevel modulation formats, electronic packet switching, electronic equalization and error correction. These methods have enabled the local area optical link data rate to increase from 0.1 Gb/s in 1990 to nearly a Tb/s in 2019. The challenges to increasing link data rates further, whilst reducing the transmitted power per bit, at reduced cost are discussed. Potential technical solutions and newly proposed methods which might address these challenges are highlighted