Verification of integer multipliers on the arithmetic bit level

One of the most severe short-comings of currently available equivalence checkers is their inability to verify integer multipliers. In this paper, we present a bit level reverse-engineering technique that can be integrated into standard equivalence checking flows. We propose a Boolean mapping algorithm that extracts a network of half adders from the gate netlist of an addition circuit. Once the arithmetic bit level representation of the circuit is obtained, equivalence checking can be performed using simple arithmetic operations. Experimental results show the promise of our approach

Highly Automated Formal Verification of Arithmetic Circuits

This dissertation investigates the problems of two distinctive formal verification techniques for verifying large scale multiplier circuits and proposes two approaches to overcome some of these problems. The first technique is equivalence checking based on recurrence relations, while the second one is the symbolic computation technique which is based on the theory of Gröbner bases. This investigation demonstrates that approaches based on symbolic computation have better scalability and more robustness than state-of-the-art equivalence checking techniques for verification of arithmetic circuits. According to this conclusion, the thesis leverages the symbolic computation technique to verify floating-point designs. It proposes a new algebraic equivalence checking, in contrast to classical combinational equivalence checking, the proposed technique is capable of checking the equivalence of two circuits which have different architectures of arithmetic units as well as control logic parts, e.g., floating-point multipliers

Efficient modular arithmetic units for low power cryptographic applications

The demand for high security in energy constrained devices such as mobiles and PDAs is growing rapidly. This leads to the need for efficient design of cryptographic algorithms which offer data integrity, authentication, non-repudiation and confidentiality of the encrypted data and communication channels. The public key cryptography is an ideal choice for data integrity, authentication and non-repudiation whereas the private key cryptography ensures the confidentiality of the data transmitted. The latter has an extremely high encryption speed but it has certain limitations which make it unsuitable for use in certain applications. Numerous public key cryptographic algorithms are available in the literature which comprise modular arithmetic modules such as modular addition, multiplication, inversion and exponentiation. Recently, numerous cryptographic algorithms have been proposed based on modular arithmetic which are scalable, do word based operations and efficient in various aspects. The modular arithmetic modules play a crucial role in the overall performance of the cryptographic processor. Hence, better results can be obtained by designing efficient arithmetic modules such as modular addition, multiplication, exponentiation and squaring. This thesis is organized into three papers, describes the efficient implementation of modular arithmetic units, application of these modules in International Data Encryption Algorithm (IDEA). Second paper describes the IDEA algorithm implementation using the existing techniques and using the proposed efficient modular units. The third paper describes the fault tolerant design of a modular unit which has online self-checking capability --Abstract, page iv

PERFORMANCE EVALUATION OF BOOTH AND WALLACE MULTIPLIER USING FIR FILTER

An area-and speed efficient multipliers is proposed in the thesis. the proposed booth and Wallace multipliers shows the tradeoff in the performance evaluation for the fir filter applications. For implementation of fir filter in this paper the adders introduced are carry save adder and carry skip adder. For evaluating the fir filter performance the tested combinations are booth carry save , booth carry skip , Wallace carry save , Wallace carry skip

Low Power and Efficient Re-Configurable Multiplier for Accelerator

Deep learning is a rising topic at the edge of technology, with applications in many areas of our lives, including object detection, speech recognition, natural language processing, and more. Deep learning's advantages of high accuracy, speed, and flexibility are now being used in practically all major sciences and technologies. As a result, any efforts to improve the performance of related techniques are worthwhile. We always have a tendency to generate data faster than we can analyse, comprehend, transfer, and reconstruct it. Demanding data-intensive applications such as Big Data. Deep Learning, Machine Learning (ML), the Internet of Things (IoT), and high- speed computing are driving the demand for "accelerators" to offload work from general-purpose CPUs. An accelerator (a hardware device) works in tandem with the CPU server to improve data processing speed and performance. There are a variety of off-the-shelf accelerator architectures available, including GPU, ASIC, and FPGA architectures. So, this work focus on designing a multiplier unit for the accelerators. This increases the performance of DNN, reduced the area and increasing the training speed of the system

Proceedings of the 21st Conference on Formal Methods in Computer-Aided Design – FMCAD 2021

The Conference on Formal Methods in Computer-Aided Design (FMCAD) is an annual conference on the theory and applications of formal methods in hardware and system verification. FMCAD provides a leading forum to researchers in academia and industry for presenting and discussing groundbreaking methods, technologies, theoretical results, and tools for reasoning formally about computing systems. FMCAD covers formal aspects of computer-aided system design including verification, specification, synthesis, and testing

High School Self-Contained Classroom: A Program Description

The purpose of this field study is the description of a program involving a self-contained classroom for those freshmen entering high school who exhibit difficulty in adjusting to the high school setting. The program seeks to aid these students in developing confidence in themselves and their decisions, improving or altering negative self-concepts, encouraging feelings of accomplishment and satisfaction in participating in high school activities, enhancing relationships with others, and emphasizing successes in the academic area. Chapter one examines the major problem areas facing students as they make the transition from the junior high to the senior high school. A major goal of the program, as stated in the needs assessment rationale, is the provision of an atmosphere whereby the student may develop more positive feelings of adequacy and self-worth as well as the realization of academic accomplishment. Included in the objectives rationale are developmental learner objectives whose aims are to facilitate the acquisition of feelings of adequacy and self-worth. Additionally, program objectives are outlined. The second chapter details a description of the program in terms of duration, scheduling of students, selection process, grading, and areas of instruction. Also, a discussion of the characteristics that may be exhibited by a student to be selected for the program is provided. Since the self-contained classroom is designed to be staffed by a certified teacher and an instructional aide, a complete job description for each is provided in the field study. Concluding chapter two is an analysis of the physical needs of the program. The final chapter examines the process of evaluating the self-contained classroom program. Methods for both student and program evaluation are presented as well as a listing of the sources of data that will be used in the process. Since the self-contained classroom is designed to provide instruction in language arts, geography, math, and general studies, course descriptions and outlines are contained in an appendix. The general studies is unique only to the self-contained classroom and will explore, use, and integrate a variety of skills that would assist the student in making the transition to the high school setting. A self-concept rating scale used in the assessment process for selection, parent permission form, teacher referral form, a checklist for evaluation purposes, and a parent evaluation form are included in additional appendicies. A bibliography containing source material on innovative programs and self-concept building concludes the study

Artificial Mixture Methods for Correlated Nominal Responses and Discrete Failure Time.

Multinomial logit model with random effects is a common choice for modeling correlated nominal responses. But due to the presence of random effects and the complex form of the multinomial probabilities, the computation is often costly. We generalize the artificial mixture method for independent nominal response to correlated nominal responses. Our method transforms the complex multinomial likelihood to Poisson-type likelihoods and hence allows for the estimates to be obtained iteratively solving a set of independent low-dimensional problems. The methodology is applied to real data and studied by simulations. For discrete failure time data in large data sets, there are often many ties and a large number of distinct event time points. This poses a challenge of a high-dimensional model. We explore two ideas with the discrete proportional odds (PO) model due to its methodological and computational convenience. The log-likelihood function of discrete PO model is the difference of two convex functions; hence difference convex algorithm (DCA) carries over and brings computational efficiency. An alternative method proposed is a recursive procedure. As a result of simulation studies, these two methods work better than Quasi-Newton method in terms of both accuracy and computational time. The results from the research on the discrete PO model motivate us to develop artificial mixture methods to discrete failure time data. We consider a general discrete transformation model and mediate the high-dimensional optimization problem by changing the model form at the “complete-data” level (conditional on artificial variables). Two complete data representations are studied: proportional hazards (PH) and PO mixture frameworks. In the PH mixture framework, we reduce the high-dimensional optimization problem to many one-dimensional problems. In the PO mixture framework, both recursive solution and DCA can be synthesized into the M-step of EM algorithm leading to simplification in the optimization. PO mixture method is recommended due to its simplicity. It is applied to real data sets to fit a discrete PH and PHPH models. Simulation study fitting discrete PH model shows that the advocated PO mixture method outperforms Quasi-Newton method in terms of both accuracy and speed.Ph.D.BiostatisticsUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/91531/1/sfwang_1.pd

Generic algorithms and NULL Convention Logic hardware implementation for unsigned and signed quad-rail multiplication

This thesis focuses on designing generic quad-rail arithmetic circuits, such as signed and unsigned multipliers and Multiply and Accumulate (MAC) units, using the asynchronous delay-insensitive NULL Convention Logic (NCL) paradigm. This work helps to build a library of reusable components to be used for automated NCL circuit synthesis, which will aid in the integration of asynchronous design paradigms into the semiconductor industry --Abstract, page iii