A circuit modeling technique for the ISO 7637-3 capacitive coupling clamp test

In this paper, we propose a transmission-line modeling technique for the ISO 7637-3 capacitive coupling clamp (CCC) test. Besides modeling the test bench, special attention is devoted to the CCC itself, for which an equivalent circuit is constructed based on the concept of surface transfer impedance and surface transfer admittance. The overall model is validated by means of measurements using a nonlinear circuit as device-under-test, as such demonstrating the appositeness to mimick the CCC test in simulations during the design phase

Overview about E-Mobility Conducted Immunity Tests on ESA Communication Lines

Due to the complexity of the Automotive Electromagnetic Compatibility legislation in force, this article aims to describe a simplified overview of several technical standards relating to conducted immunity tests on electronic sub-assemblies, where communication lines are involved. The discussed automotive standards reported in this article are: ISO 11452-1 and ISO 11452-4 for continuous narrowband electromagnetic fields immunity test, bulk current injection and tubular wave coupler, IEC 61000-4-5 for immunity against surge events, IEC 61000-4-4 for electrical fast transient/burst events immunity, ISO 10605 for electrostatic discharge events immunity, ISO 7637-2 and ISO 7637-3 for transient disturbances events immunity. For each cited standard, disturbance bandwidth evaluation was performed. Practical examples are reported, with analysis and discussion of some of the adoptable disturbance countermeasures applicable on controlled area network communication lines, and possible design advantages and disadvantages with different types of filtering and suppression circuit solutions

Lightning testing at the subsystem level

Testing at the subsystem or black box level for lightning hardness is required if system hardness is to be assured at the system level. The often applied philosophy of lighting testing only at the system level leads to extensive end of the line design changes which result in excessive costs and time delays. In order to perform testing at the subsystem level two important factors must be defined to make the testing simulation meaningful. The first factor is the definition of the test stimulus appropriate to the subsystem level. Application of system level stimulations to the subsystem level usually leads to significant overdesign of the subsystem which is not necessary and may impair normal subsystem performance. The second factor is the availability of test equipment needed to provide the subsystem level lightning stimulation. Equipment for testing at this level should be portable or at least movable to enable efficient testing in a design laboratory environment. Large fixed test installations for system level tests are not readily available for use by the design engineers at the subsystem level and usually require special operating skills. The two factors, stimulation level and test equipment availability, must be evaluated together in order to produce a practical, workable test standard. The neglect or subordination of either factor will guarantee failure in generating the standard. It is not unusual to hear that test standards or specifications are waived because a specified stimulation level cannot be accomplished by in-house or independent test facilities. Determination of subsystem lightning simulation level requires a knowledge and evaluation of field coupling modes, peak and median levels of voltages and currents, bandwidths, and repetition rates. Practical limitations on test systems may require tradeoffs in lightning stimulation parameters in order to build practical test equipment. Peak power levels that can be generated at specified bandwidths with standard electrical components must be considered in the design and costing of the test system. Stimulation tests equipment and test methods are closely related and must be considered a test system for lightning simulation. A non-perfect specification that can be reliably and repeatedly applied at the subsystem test level is more desirable than a perfect specification that cannot be applied at all

Characterization of noncontact piezoelectric transducer with conically shaped piezoelement

The characterization of a dynamic surface displacement transducer (IQI Model 501) by a noncontact method is presented. The transducer is designed for ultrasonic as well as acoustic emission measurements and, according to the manufacturer, its characteristic features include a flat frequency response range which is from 50 to 1000 kHz and a quality factor Q of less than unity. The characterization is based on the behavior of the transducer as a receiver and involves exciting the transducer directly by transient pulse input stress signals of quasi-electrostatic origin and observing its response in a digital storage oscilloscope. Theoretical models for studying the response of the transducer to pulse input stress signals and for generating pulse stress signals are presented. The characteristic features of the transducer which include the central frequency f sub o, quality factor Q, and flat frequency response range are obtained by this noncontact characterization technique and they compare favorably with those obtained by a tone burst method which are also presented

Design of a fast computer-based partial discharge diagnostic system

Partial discharges cause progressive deterioration of insulating materials working in high voltage conditions and may lead ultimately to insulator failure. Experimental findings indicate that deterioration increases with the number of discharges and is consequently proportional to the magnitude and frequency of the applied voltage. In order to obtain a better understanding of the mechanisms of deterioration produced by partial discharges, instrumentation capable of individual pulse resolution is required. A new computer-based partial discharge detection system was designed and constructed to conduct long duration tests on sample capacitors. This system is capable of recording large number of pulses without dead time and producing valuable information related to amplitude, polarity, and charge content of the discharges. The operation of the system is automatic and no human supervision is required during the testing stage. Ceramic capacitors were tested at high voltage in long duration tests. The obtained results indicated that the charge content of partial discharges shift towards high levels of charge as the level of deterioration in the capacitor increases

Development of a Supercapacitor based Surge Resistant Uninterruptible Power Supply

Uninterruptible Power Supplies (UPSs) provide short-term power back-up to sensitive electronic and electrical equipments, where an unexpected power loss could lead to undesirable outcomes. They usually bridge the connected equipment between the utility mains power and other long term back-up power systems like generators. A UPS also provides a “clean” source of power, meaning they filter the connected equipment from distortions in electrical parameters of the mains power like noise, harmonics, surges, sags and spikes. A surge resistant UPS or SRUPS is one that has the capability to withstand surges, which are momentary or sustained increases in the mains voltage, and react quickly enough to offer protection to the connected equipment from the same. Usually UPSs run off battery power when the utility mains power is absent. But the SRUPS developed in this design project uses super capacitors instead of battery packs. The reason for this is that the high energy-densities and medium power-densities offered by super capacitors allow for it to serve two purposes. One is to provide the DC power to operate the UPS in the absence of mains power, as an alternative to batteries. Secondly, super capacitors can withstand heavy momentary high current/voltage surges due to its high energy-density characteristics. Also as the life-time of super capacitors is much higher than that of conventional batteries and as they do not need regular topping-up or inspection, the end result is a truly maintenance-free UPS. Most commercial UPSs do not have inherent surge protection capabilities. The UPS is one entity while a discrete surge protection module is inserted between the utility mains and the UPS to provide for transient surge suppression. In the proposed SRUPS, the super capacitor, because of their inherent capability to absorb transient surges, forms a protective front end to the actual UPS rather than needing to have the involvement of discrete protection devices

System and IC level analysis of electrostatic discharge (ESD) and electrical fast transient (EFT) immunity and associated coupling mechanisms

The exposure of electronic circuits to lightning, electrostatic discharge (ESD), electrical fast transients (EFT) or sine wave signals can reveal RF immunity problems. Typical problems include temporary malfunctions or permanent damage of integrated circuits (ICs). In an effort to reproduce those disturbances, a series of electromagnetic compatibility standards has been developed. However, a complete understanding of the root cause of the immunity problems has yet to be established. This dissertation discusses immunity problems in three papers, starting at the system level, via the coupling path into the IC --Abstract, page iv

Bubble memory module

Design, fabrication and test of partially populated prototype recorder using 100 kilobit serial chips is described. Electrical interface, operating modes, and mechanical design of several module configurations are discussed. Fabrication and test of the module demonstrated the practicality of multiplexing resulting in lower power, weight, and volume. This effort resulted in the completion of a module consisting of a fully engineered printed circuit storage board populated with 5 of 8 possible cells and a wire wrapped electronics board. Interface of the module is 16 bits parallel at a maximum of 1.33 megabits per second data rate on either of two interface buses

Far-field prediction using only magnetic near-field scanning and modeling delay variations in CMOS digital logic circuits due to electrical disturbances in the power supply

The first topic of this dissertation is far-field prediction using only magnetic near-field scanning. Near-field scanning has been used extensively for the far-field estimation of antennas. Applied to electromagnetic compatibility (EMC) problems, near-field scanning has been used to estimate emissions from both integrated circuits (ICs) and printed circuit boards (PCBs). Interest in applying far-field predictions using near-field to EMI/EMC problems has recently grown. To predict the far-field emissions from a PCB in the top half space, the near-field data on a planar surface above PCB usually is sufficient. However, near-field measurement on only one planar surface may not be enough to predict the far-field radiation of three-dimensional structures. The near-field on an enclosed Huygens\u27s surface may be preferred for near-field scanning when predicting the far-field radiation associated with the EMI problems of some complex structures. Based on the equivalence theorem (Huygens\u27s principle), both equivalent electric current obtained from the tangential magnetic field and equivalent magnetic current obtained from the tangential electric field are needed to perform far-field transformation from near-field data. However, designing electric field probes for tangential components is more difficult than designing magnetic field probes. As a result and in the interest of reducing scan time, far-field transformation based only on magnetic field near-field measurements is preferred. In the first paper, a novel method is proposed to predict the far-field radiation using only the magnetic near-field component on a Huygens\u27s box. The proposed method was verified with two simulated examples and one measurement case. The effect of inaccuracy of magnetic field and the incompleteness of the Huygens\u27s box on far-field results is investigated in this paper. The proposed method can be applied for arbitrary shapes of closed Huygens\u27s surfaces. Only the tangential magnetic field needs to be measured. And it also shows good accuracy and robustness in use. Measuring only the magnetic field cuts the scan time in half. The second topic of this dissertation is modeling delay variations in CMOS digital logic circuits due to electrical disturbances in the power supply. Electronic designers go to considerable effort to minimize the susceptibility of electronic systems against electromagnetic interference. For many systems, the component which fails is an integrated circuit (IC). Susceptibilities are typically found through testing, which is expensive, time consuming, and does not always uncover problems that are encountered in the field. While IC-level testing helps to establish the operational limits of an IC, testing rarely ensures the IC can withstand all interferences, even within the specified limits. Even when a problem is found, the engineer often does not know why a problem was caused or the best way to prevent the problem in the future. Solving problems through trial and error cannot be done as it is at the system level, because of the prohibitive cost of manufacturing and testing multiple versions of the IC. The IC engineer must build the IC to be robust on the first design cycle. IC failures may be caused by a hard failure of the IC, for example, due to latch-up or permanent damage to an I/O pin, or may be caused by a soft failure, where incorrect data is read from I/O, internal logic, and/or memory. Soft errors that occur within the logic and/or memory components of the IC can be particularly difficult to deal with since errors associated with these components are much more diverse and complex than those associated with I/O. One common reason for soft errors is that a change in the power supply voltage causes a change in the propagation delay through internal logic or the clock tree, so that the clock edge arrives at a register before valid data and an incorrect logic value is stored at the register. While methods are available to predict the level of voltage fluctuation within the IC from an external electromagnetic event, predicting when a failure will occur as a result of the event is challenging. Methods are developed in the second paper and third paper to help predict these soft failures, by predicting the change in the propagation delay through logic during an electromagnetic disturbance of the power supply. In the second paper, an analytical delay model was developed to predict propagation delay variations in logic circuits when the power supply is disturbed by an electromagnetic event. Simulated and measured results demonstrate the accuracy of the approach. Four different types of logic circuits were tested, verifying that the proposed delay model can be applied to a wide range of logic circuits and process technologies. Analytical formulas were developed to predict the clock period variation in integrate circuit when the power supply is disturbed by an electromagnetic event in the third paper. The proposed formulas can be seen as a clock jitter model. The clock jitter due to the power supply variation can be estimated by the proposed propagation delay model. It is more meaningful, however, to estimate the clock period variation rather than the delay variation for one clock edge, because it is clock period which affects if a soft error will happen or not. Simulated results using Cadence Virtuoso demonstrate the validity and accuracy of the proposed approach. Three different types of noise were used to disturb the power supply voltage, verifying that the proposed model can be applied to a wide range of disturbance of power supply. Many electromagnetic events cause soft errors in ICs by momentarily disturbing the power supply voltage. The proposed model can be helpful for predicting and understanding the soft errors caused by these timing changes within the logic --Abstract, page iv