Embracing the Unreliability of Memory Devices for Neuromorphic Computing

The emergence of resistive non-volatile memories opens the way to highly energy-efficient computation near- or in-memory. However, this type of computation is not compatible with conventional ECC, and has to deal with device unreliability. Inspired by the architecture of animal brains, we present a manufactured differential hybrid CMOS/RRAM memory architecture suitable for neural network implementation that functions without formal ECC. We also show that using low-energy but error-prone programming conditions only slightly reduces network accuracy

Self-Testing Analog Spiking Neuron Circuit

International audienceHardware-implemented neural networks are foreseen to play an increasing role in numerous applications. In this paper, we address the problem of post-manufacturing test and self-test of hardware-implemented neural networks. In particular, we propose a self-testable version of a spiking neuron circuit. The self-test wrapper is a compact circuit composed of a low-precision ramp generator and a small digital block. The self-test principle is demonstrated on a spiking neuron circuit design in 0.35µm CMOS technology

Charge-Trapping-Induced Compensation of the Ferroelectric Polarization in FTJs: Optimal Conditions for a Synaptic Device Operation

In this work, we present a clear evidence, based on numerical simulations and experiments, that the polarization compensation due to trapped charge strongly influences the ON/ OFF ratio in Hf 0.5 Zr 0.5 O 2 (HZO)-based ferroelectric tunnel junctions (FTJs). Furthermore, we identify and explain compensation conditions that enable an optimal operation of FTJs. Our results provide both key physical insights and design guidelines for the operation of FTJs as multilevel synaptic devices

Current localisation and redistribution as the basis of discontinuous current controlled negative differential resistance in NbOx

In-situ thermo-reflectance imaging is used to show that the discontinuous, snap-back mode of current-controlled negative differential resistance (CC-NDR) in NbOx-based devices is a direct consequence of current localization and redistribution. Current localisation is shown to result from the creation of a conductive filament either during electroforming or from current bifurcation due to the super-linear temperature dependence of the film conductivity. The snap-back response then arises from current redistribution between regions of low and high current-density due to the rapid increase in conductivity created within the high current density region. This redistribution is further shown to depend on the relative resistance of the low current-density region with the characteristics of NbOx cross-point devices transitioning between continuous and discontinuous snap-back modes at critical values of film conductivity, area, thickness and temperature, as predicted. These results clearly demonstrate that snap-back is a generic response that arises from current localization and redistribution within the oxide film rather than a material-specific phase transition, thus resolving a long-standing controversy.Comment: 21 Page