2,474 research outputs found
Effective electrothermal analysis of electronic devices and systems with parameterized macromodeling
We propose a parameterized macromodeling methodology to effectively and accurately carry out dynamic electrothermal (ET) simulations of electronic components and systems, while taking into account the influence of key design parameters on the system behavior. In order to improve the accuracy and to reduce the number of computationally expensive thermal simulations needed for the macromodel generation, a decomposition of the frequency-domain data samples of the thermal impedance matrix is proposed. The approach is applied to study the impact of layout variations on the dynamic ET behavior of a state-of-the-art 8-finger AlGaN/GaN high-electron mobility transistor grown on a SiC substrate. The simulation results confirm the high accuracy and computational gain obtained using parameterized macromodels instead of a standard method based on iterative complete numerical analysis
Physics-based large-signal sensitivity analysis of microwave circuits using technological parametric sensitivity from multidimensional semiconductor device models
The authors present an efficient approach to evaluate the large-signal (LS) parametric sensitivity of active semiconductor devices under quasi-periodic operation through accurate, multidimensional physics-based models. The proposed technique exploits efficient intermediate mathematical models to perform the link between physics-based analysis and circuit-oriented simulations, and only requires the evaluation of dc and ac small-signal (dc charge) sensitivities under general quasi-static conditions. To illustrate the technique, the authors discuss examples of sensitivity evaluation, statistical analysis, and doping profile optimization of an implanted MESFET to minimize intermodulation which makes use of LS parametric sensitivities under two-tone excitatio
CMOS design of chaotic oscillators using state variables: a monolithic Chua's circuit
This paper presents design considerations for monolithic implementation of piecewise-linear (PWL) dynamic systems in CMOS technology. Starting from a review of available CMOS circuit primitives and their respective merits and drawbacks, the paper proposes a synthesis approach for PWL dynamic systems, based on state-variable methods, and identifies the associated analog operators. The GmC approach, combining quasi-linear VCCS's, PWL VCCS's, and capacitors is then explored regarding the implementation of these operators. CMOS basic building blocks for the realization of the quasi-linear VCCS's and PWL VCCS's are presented and applied to design a Chua's circuit IC. The influence of GmC parasitics on the performance of dynamic PWL systems is illustrated through this example. Measured chaotic attractors from a Chua's circuit prototype are given. The prototype has been fabricated in a 2.4- mu m double-poly n-well CMOS technology, and occupies 0.35 mm/sup 2/, with a power consumption of 1.6 mW for a +or-2.5-V symmetric supply. Measurements show bifurcation toward a double-scroll Chua's attractor by changing a bias current
Towards a microscopic understanding of phonon heat conduction
Heat conduction by phonons is a ubiquitous process that incorporates a wide
range of physics and plays an essential role in applications ranging from space
power generation to LED lighting. Heat conduction has been studied for over two
hundred years, yet many microscopic aspects of heat conduction have remained
unclear in most crystalline solids, including which phonons carry heat and how
natural and artificial structures scatter specific phonons. Fortunately, recent
advances in both computation and experiment are enabling an unprecedented
microscopic view of thermal transport by phonons. In this topical review, we
provide an overview of these methods, the insights they are providing, and
their impact on the science and engineering of heat conduction
Tensor Computation: A New Framework for High-Dimensional Problems in EDA
Many critical EDA problems suffer from the curse of dimensionality, i.e. the
very fast-scaling computational burden produced by large number of parameters
and/or unknown variables. This phenomenon may be caused by multiple spatial or
temporal factors (e.g. 3-D field solvers discretizations and multi-rate circuit
simulation), nonlinearity of devices and circuits, large number of design or
optimization parameters (e.g. full-chip routing/placement and circuit sizing),
or extensive process variations (e.g. variability/reliability analysis and
design for manufacturability). The computational challenges generated by such
high dimensional problems are generally hard to handle efficiently with
traditional EDA core algorithms that are based on matrix and vector
computation. This paper presents "tensor computation" as an alternative general
framework for the development of efficient EDA algorithms and tools. A tensor
is a high-dimensional generalization of a matrix and a vector, and is a natural
choice for both storing and solving efficiently high-dimensional EDA problems.
This paper gives a basic tutorial on tensors, demonstrates some recent examples
of EDA applications (e.g., nonlinear circuit modeling and high-dimensional
uncertainty quantification), and suggests further open EDA problems where the
use of tensor computation could be of advantage.Comment: 14 figures. Accepted by IEEE Trans. CAD of Integrated Circuits and
System
Mixed-signal CNN array chips for image processing
Due to their local connectivity and wide functional capabilities, cellular nonlinear networks (CNN) are excellent candidates for the implementation of image processing algorithms using VLSI analog parallel arrays. However, the design of general purpose, programmable CNN chips with dimensions required for practical applications raises many challenging problems to analog designers. This is basically due to the fact that large silicon area means large development cost, large spatial deviations of design parameters and low production yield. CNN designers must face different issues to keep reasonable enough accuracy level and production yield together with reasonably low development cost in their design of large CNN chips. This paper outlines some of these major issues and their solutions
VLSI Design
This book provides some recent advances in design nanometer VLSI chips. The selected topics try to present some open problems and challenges with important topics ranging from design tools, new post-silicon devices, GPU-based parallel computing, emerging 3D integration, and antenna design. The book consists of two parts, with chapters such as: VLSI design for multi-sensor smart systems on a chip, Three-dimensional integrated circuits design for thousand-core processors, Parallel symbolic analysis of large analog circuits on GPU platforms, Algorithms for CAD tools VLSI design, A multilevel memetic algorithm for large SAT-encoded problems, etc
Towards Multidimensional Verification: Where Functional Meets Non-Functional
Trends in advanced electronic systems' design have a notable impact on design
verification technologies. The recent paradigms of Internet-of-Things (IoT) and
Cyber-Physical Systems (CPS) assume devices immersed in physical environments,
significantly constrained in resources and expected to provide levels of
security, privacy, reliability, performance and low power features. In recent
years, numerous extra-functional aspects of electronic systems were brought to
the front and imply verification of hardware design models in multidimensional
space along with the functional concerns of the target system. However,
different from the software domain such a holistic approach remains
underdeveloped. The contributions of this paper are a taxonomy for
multidimensional hardware verification aspects, a state-of-the-art survey of
related research works and trends towards the multidimensional verification
concept. The concept is motivated by an example for the functional and power
verification dimensions.Comment: 2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP
and International Symposium of System-on-Chip (SoC
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