Basic Block of Pipelined ADC Design Requirements

The paper describes design requirements of a basic stage (called MDAC - Multiplying Digital-to- Analog Converter) of a pipelined ADC. There exist error sources such as finite DC gain of opamp, capacitor mismatch, thermal noise, etc., arising when the switched capacitor (SC) technique and CMOS technology are used. These non-idealities are explained and their influences on overall parameters of a pipelined ADC are studied. The pipelined ADC including non-idealities was modeled in MATLAB - Simulink simulation environment

Entwurfsregeln für supraleitende Analog-Digital-Wandler

This Thesis is a contribution for dimensioning aspects of circuits designs in superconductor electronics. Mainly superconductor comparators inclusive Josephson comparators as well as QOJS-Comparators are investigated. Both types were investigated in terms of speed and sensitivity. The influence of the thermal noise on the decision process of the comparators represent in so called gray zone, which is analysed in this thesis. Thereby, different relations between design parameters were derived. A circuit model of the Josephson comparator was verified by experiments. Concepts of superconductor analog-to-digital converters, which are based on above called comparators, were investigated in detail. From the comparator design rules, new rules for AD-converters were derived. Because of the reduced switching energy, the signal to noise ratio (SNR) of the circuits is affected and therefore the reliability of the decision-process is affected. For special applications with very demanding requirements in terms of the speed and accuracy superconductor analog-to-digital converters offer an excellent performance. This thesis provides relations between different design paramenters and shows resulting trade-offs, This method is transparent and easy to transfer to other circuit topologies. As a main result, a highly predictive tool for dimensioning of superconducing ADC's is proved.Die vorliegende Dissertationsschrift liefert einen Beitrag zu Dimensionierungsaspekten des Schaltungsentwurfs in der supraleitender Elektronik. Dazu werden supraleitende Komparatoren, d. h. Josephson-Komparator und QOJS-Komparator bezüglich der Geschwindigkeit und der Empfindlichkeit untersucht. Der Einfluss des thermischen Rauschens auf den Entscheidungsprozess der Komparatoren repräsentiert die so genannte Grauzone. Sie wird in der Arbeit als wichtige Kennzahl ausführlich analysiert. Daraus werden verschiedene Parameterabhängigkeiten dargestellt. Eine Modellierung eines Josephson-Komparator wurde experimentell bestätigt. Darauf aufbauend werden Konzepte von supraleitenden Analog-Digital-Wandlern in der Arbeit untersucht und daraus Entwurfsregeln abgeleitet. Durch die Reduzierung der Schaltenegie wird das Signal-Rausch-Verhältnis (SNR) der Schaltungen und damit die Zuverlässigkeit von Entscheidungsprozessen und Schaltvorgängen beeinflusst. Für Spezialanwendungen mit sehr hohen Anforderungen bezüglich der Geschwindigkeit oder Genauigkeit bieten supraleitende AD-Wandler ausgezeichnete Leistungsmerkmale an. Die Arbeit liefert konkrete Zusammenhänge zwischen den unterschiedlichen Entwurfsparametern und zeigt mögliche Kompromisse auf. Die Methoden sind transparent dargestellt und lassen sich leicht auf andere Schaltungstopologien übertragen. Im Ergebnis wird ein Werkzeug zur objektiven Dimensionierung von supraleitenden AD-Wandlern bereitgestellt

Digital Background Self-Calibration Technique for Compensating Transition Offsets in Reference-less Flash ADCs

This Dissertation focusses on proving that background calibration using adaptive algorithms are low-cost, stable and effective methods for obtaining high accuracy in flash A/D converters. An integrated reference-less 3-bit flash ADC circuit has been successfully designed and taped out in UMC 180 nm CMOS technology in order to prove the efficiency of our proposed background calibration. References for ADC transitions have been virtually implemented built-in in the comparators dynamic-latch topology by a controlled mismatch added to each comparator input front-end. An external very simple DAC block (calibration bank) allows control the quantity of mismatch added in each comparator front-end and, therefore, compensate the offset of its effective transition with respect to the nominal value. In order to assist to the estimation of the offset of the prototype comparators, an auxiliary A/D converter with higher resolution and lower conversion speed than the flash ADC is used: a 6-bit capacitive-DAC SAR type. Special care in synchronization of analogue sampling instant in both ADCs has been taken into account. In this thesis, a criterion to identify the optimum parameters of the flash ADC design with adaptive background calibration has been set. With this criterion, the best choice for dynamic latch architecture, calibration bank resolution and flash ADC resolution are selected. The performance of the calibration algorithm have been tested, providing great programmability to the digital processor that implements the algorithm, allowing to choose the algorithm limits, accuracy and quantization errors in the arithmetic. Further, systematic controlled offset can be forced in the comparators of the flash ADC in order to have a more exhaustive test of calibration

Time interleaved counter analog to digital converters

The work explores extending time interleaving in A/D converters, by applying a high-level of parallelism to one of the slowest and simplest types of data-converters, the counter ADC. The motivation for the work is to realise high-performance re-configurable A/D converters for use in multi-standard and multi-PHY communication receivers with signal bandwidths in the 10s to 100s of MHz. The counter ADC requires only a comparator, a ramp signal, and a digital counter, where the comparator compares the sampled input against all possible quantisation levels sequentially. This work explores arranging counter ADCs in large time-interleaved arrays, building a Time Interleaved Counter (TIC) ADC. The key to realising a TIC ADC is distributed sampling and a global multi-phase ramp generator realised with a novel figure-of-8 rotating resistor ring. Furthermore Counter ADCs allow for re-configurability between effective sampling rate and resolution due to their sequential comparison of reference levels in conversion. A prototype TIC ADC of 128-channels was fabricated and measured in 0.13μm CMOS technology, where the same block can be configured to operate as a 7-bit 1GS/s, 8-bit 500MS/s, or 9-bit 250MS/s dataconverter. The ADC achieves a sub 400fJ/step FOM in all modes of configuration