Low-power spatial computing using dynamic threshold devices

Asynchronous spatial computing systems exhibit only localized communication, their overall data-flow being controlled by handshaking. It is therefore straightforward to determine when a particular part of such a system is active. We show that using thin-body double-gate fully depleted SOI transistors, the shift in threshold voltage that can be produced by modulating the back-gate bias is sufficient to reduce subthreshold leakage power by a factor of more than 104 in typical circuits. Using TBFDSOI devices in spatial computing architectures will allow overall power to be greatly reduced while maintaining high performance

Why area might reduce power in nanoscale CMOS

In this paper we explore the relationship between power and area. By exploiting parallelism (and thus using more area) one can reduce the switching frequency allowing a reduction in VDD which results in a reduction in power. Under a scaling regime which allows threshold voltage to increase as VDD decreases we find that dynamic and subthreshold power loss in CMOS exhibit a dependence on area proportional to A(s-3)s/ while gate leakage power ? A(s-6)s/, and short circuit power ? A(s-8)s/. Thus, with the large number of devices at our disposal we can exploit techniques such as spatial computing, tailoring the program directly to the hardware, to overcome the negative effects of scaling. The value of s describes the effectiveness of the technique for a particular circuit and/or algorithm - for circuits that exhibit a value of s =3, power will be a constant or reducing function of area. We briefly speculate on how s might be influenced by a move to nanoscale technology

Impact of Device Parameteres of Triple Gate SOI-FINFET on the Performance of CMOS Inverter at 22NM

A simulation based design evaluation is reported for SOI FinFETs at 22nm gate length. The impact of device parameters on the static power dissipation and delay of a CMOS inverter is presented. Fin dimensions such as Fin width and height are varied. For a given gate oxide thickness increasing the fin height and fin width degrades the SCEs, while improves the performance. It was found that reducing the fin thickness was beneficial in reducing the off state leakage current (IOFF), while reducing the fin height was beneficial in reducing the gate leakage current (IGATE). It was found that Static power dissipation of the inverter increases with fin height due to the increase in leakage current, whereas delay decreased with increase fin width due to higher on current. The performance of the inverter decreased with the down scaling of the gate oxide thickness due to higher gate leakage current and gate capacitance

Compact modeling of gate tunneling leakage current in advanced nanoscale soi mosfets

En esta tesis se han desarrollado modelos compactos de corriente de fuga por túnel de puerta en SOI MOSFET (de simple y doble puerta) avanzados basados en una aproximación WKB de la probabilidad de túnel. Se han estudiado los materiales dieléctricos high-k más prometedores para los diferentes requisitos de nodos tecnológicos de acuerdo ala hoja de ruta ITRS de miniaturización de dispositivos electrónicos. Hemos presentado un modelo compacto de particionamiento de la corriente de fuga de puerta para un MOSFET nanométrico de doble puerta (DG MOSFET), utilizando modelos analíticos de la corriente de fuga por el túnel directo de puerta. Se desarrollaron también Los modelos analíticos dependientes de la temperatura de la corriente de túnel en la región de inversión y de la corriente túnel asistido por trampas en régimen subumbral. Finalmente, se desarrolló una técnica de extracción automática de parámetros de nuestro modelo compacto en DG MOSFET incluyendo efectos de canal corto. La corriente de la puerta por túnel directo y asistido por trampas modelada mediante los parámetros extraídos se verificó exitosamente mediante comparación con medidas experimentales