SCERPA Simulation of Clocked Molecular Field-Coupling Nanocomputing

Among all the possible technologies proposed for post-CMOS computing, molecular field-coupled nanocomputing (FCN) is one of the most promising technologies. The information propagation relies on electrostatic interactions among single molecules, overcoming the need for electron transport, significantly reducing energy dissipation. The expected working frequency is very high, and high throughput may be achieved by introducing an efficient pipeline of information propagation. The pipeline could be realized by adding an external clock signal that controls the propagation of data and makes the transmission adiabatic. In this article, we extend the Self-Consistent Electrostatic Potential Algorithm (SCERPA), previously introduced to analyze molecular circuits with a uniform clock field, to clocked molecular devices. The single-molecule is analyzed by ab initio calculations and modeled as an electronic device. Several clocked devices have been partitioned into clock zones and analyzed: the binary wire, the bus, the inverter, and the majority voter. The proposed modification of SCERPA enables linking the functional behavior of the clocked devices to molecular physics, becoming a possible tool for the eventual physical design verification of emerging FCN devices. The algorithm provides some first quantitative results that highlight the clocked propagation characteristics and provide significant feedback for the future implementation of molecular FCN circuits

Investigation of Molecular FCN for Beyond-CMOS: Technology, design, and modeling for nanocomputing

L'abstract è presente nell'allegato / the abstract is in the attachmen

Hybrid Quantum-Dot Cellular Automata Nanocomputing Circuits

Quantum-dot cellular automata (QCA) is an emerging transistor-less field-coupled nanocomputing (FCN) approach to ultra-scale ‘nanochip’ integration. In QCA, to represent digital circuitry, electrostatic repulsion between electrons and the mechanism of electron tunnelling in quantum dots are used. QCA technology can surpass conventional complementary metal oxide semiconductor (CMOS) technology in terms of clock speed, reduced occupied chip area, and energy efficiency. To develop QCA circuits, irreversible majority gates are typically used as the primary components. Recently, some studies have introduced reversible design techniques, using reversible majority gates as the main building block, to develop ultra-energy-efficient QCA circuits. However, this approach resulted in time delays, an increase in the number of QCA cells used, and an increase in the chip area occupied. This work introduces a novel hybrid design strategy employing irreversible, reversible, and partially reversible QCA gates to establish an optimal balance between power consumption, delay time, and occupied area. This hybrid technique allows the designer to have more control over the circuit characteristics to meet different system needs. A combination of reversible, irreversible, and innovative partially reversible majority gates is used in the proposed hybrid design method. We evaluated the hybrid design method by examining the half-adder circuit as a case study. We developed four hybrid QCA half-adder circuits, each of which simultaneously incorporates various types of majority gates. The QCADesigner-E 2.2 simulation tool was used to simulate the performance and energy efficiency of the half-adders. This tool provides numerical results for the circuit input/output response and heat dissipation at the physical level within a microscopic quantum mechanical model.N/

FUNCODE: Effective Device-to-System Analysis of Field Coupled Nanocomputing Circuit Designs

Many beyond-CMOS technologies, based on different switching mechanisms, are arising. Field-coupled technologies are the most promising as they can guarantee an extremely low-power consumption and combine logic and memory into the same device. However, circuit-level explorations, like layout verification and analysis of the circuit performance, considering the constraints of the target technology, cannot be done using existing tools. Here, we propose a methodology to take on this challenge. We present FUNCODE (FUNction & COnnection DEtection), an algorithm that can detect element connections, functions and errors of custom-layouts and generate its corresponding VHDL netlist. It is proposed for in-plane and perpendicular Nano Magnetic Logic as a case study. FUNCODE netlists, which take into account the physical behavior of the technology, were verified using circuits with increasing complexity, from 6 up to 1400 gates with a number of layout elements varying from 200 to 2.3e6

Studying the effects of intermittent faults on a microcontroller

As CMOS technology scales to the nanometer range, designers have to deal with a growing number and variety of fault types. Particularly, intermittent faults are expected to be an important issue in modern VLSI circuits. The complexity of manufacturing processes, producing residues and parameter variations, together with special aging mechanisms, may increase the presence of such faults. This work presents a case study of the impact of intermittent faults on the behavior of a commercial microcontroller. In order to carry out an exhaustive reliability assessment, the methodology used lies in VHDL-based fault injection technique. In this way, a set of intermittent fault models at logic and register transfer abstraction levels have been generated and injected in the VHDL model of the system. From the simulation traces, the occurrences of failures and latent errors have been logged. The impact of intermittent faults has been also compared to that got when injecting transient and permanent faults. Finally, some injection experiments have been reproduced in a RISC microprocessor and compared with those of the microcontroller. © 2012 Elsevier Ltd. All rights reserved.This work has been funded by the Spanish Government under the Research Project TIN2009-13825.Gil Tomás, DA.; Gracia-Morán, J.; Baraza Calvo, JC.; Saiz-Adalid, L.; Gil Vicente, PJ. (2012). Studying the effects of intermittent faults on a microcontroller. Microelectronics Reliability. 52(11):2837-2846. https://doi.org/10.1016/j.microrel.2012.06.004S28372846521

Effects of intermittent faults on the reliability of a Reduced Instruction Set Computing (RISC) microprocessor

© 2014 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.With the scaling of complementary metal-oxide-semiconductor (CMOS) technology to the submicron range, designers have to deal with a growing number and variety of fault types. In this way, intermittent faults are gaining importance in modern very large scale integration (VLSI) circuits. The presence of these faults is increasing due to the complexity of manufacturing processes (which produce residues and parameter variations), together with special aging mechanisms. This work presents a case study of the impact of intermittent faults on the behavior of a reduced instruction set computing (RISC) microprocessor. We have carried out an exhaustive reliability assessment by using very-high-speed-integrated-circuit hardware description language (VHDL)-based fault injection. In this way, we have been able to modify different intermittent fault parameters, to select various targets, and even, to compare the impact of intermittent faults with those induced by transient and permanent faults.This work was supported by the Spanish Government under the Research Project TIN2009-13825 and by the Universitat Politecnica de Valencia under the Project SP20120806. Associate Editor: L. Cui.Gracia-Morán, J.; Baraza Calvo, JC.; Gil Tomás, DA.; Saiz-Adalid, L.; Gil, P. (2014). Effects of intermittent faults on the reliability of a Reduced Instruction Set Computing (RISC) microprocessor. IEEE Transactions on Reliability. 63(1):144-153. https://doi.org/10.1109/TR.2014.2299711S14415363

Sub-nanosecond signal propagation in anisotropy engineered nanomagnetic logic chains

Energy efficient nanomagnetic logic (NML) computing architectures propagate and process binary information by relying on dipolar field coupling to reorient closely-spaced nanoscale magnets. Signal propagation in nanomagnet chains of various sizes, shapes, and magnetic orientations has been previously characterized by static magnetic imaging experiments with low-speed adiabatic operation; however the mechanisms which determine the final state and their reproducibility over millions of cycles in high-speed operation (sub-ns time scale) have yet to be experimentally investigated. Monitoring NML operation at its ultimate intrinsic speed reveals features undetectable by conventional static imaging including individual nanomagnetic switching events and systematic error nucleation during signal propagation. Here, we present a new study of NML operation in a high speed regime at fast repetition rates. We perform direct imaging of digital signal propagation in permalloy nanomagnet chains with varying degrees of shape-engineered biaxial anisotropy using full-field magnetic soft x-ray transmission microscopy after applying single nanosecond magnetic field pulses. Further, we use time-resolved magnetic photo-emission electron microscopy to evaluate the sub-nanosecond dipolar coupling signal propagation dynamics in optimized chains with 100 ps time resolution as they are cycled with nanosecond field pulses at a rate of 3 MHz. An intrinsic switching time of 100 ps per magnet is observed. These experiments, and accompanying macro-spin and micromagnetic simulations, reveal the underlying physics of NML architectures repetitively operated on nanosecond timescales and identify relevant engineering parameters to optimize performance and reliability.Comment: Main article (22 pages, 4 figures), Supplementary info (11 pages, 5 sections