Significant papers from the First 25 Years of the FPL Conference

The list of significant papers from the first 25 years of the Field-Programmable Logic and Applications conference (FPL) is presented in this paper. These 27 papers represent those which have most strongly influenced theory and practice in the field.postprin

Automatic High-Level Hardware Checkpoint Selection for Reconfigurable Systems

International audience—Modern FPGAs provide great computational power and flexibility but there is still room for improving their performances. For example multiuser approaches are particularly underdeveloped as they require specific mechanisms still to be automated. Sharing an FPGA resource between applications or users requires a context switch ability. The latter enables pausing and resuming applications at system demand. This paper presents a method that automatically selects a good execution point, called hardware checkpoint, to perform a context switch on an FPGA. The method relies on a static analysis of the finite state machine of a circuit to select the checkpoint states. The obtained selection ensures that the context switch mechanism respects a given latency and tries to minimize the mechanism costs. The method takes advantage of its integration in an open-source HLS tool and preliminary results highlight its efficiency. Index Terms—FPGA, HLS, CAD, hardware context switc

Flot de conception automatique pour circuits commutables

National audienceLes FPGA, ou puces reconfigurables, n’ont pas cessé d’évoluer depuis leur création et sont désormais utilisés dans des systèmes complets (Xilinx Zynq ou Altera Stratix). Malgré tout, il reste de nombreux champs applicatifs desquels ils sont absents, et à tort. Utiliser les FPGA de manière plus intense au sein de systèmes complets est possible, mais il faut pour cela développer les capacités multi-utilisateurs de ces plateformes. Donner la capacité à une application s’exécutant sur un FPGA de se stopper pour, par exemple, laisser s’exécuter d’autres applications jugées prioritaires est particulièrement intéressant. Une telle action est qualifiée de « changement de contexte » (en anglais context-switch).Dans cet article, nous présentons une méthode et un outil permettant de donner cette capacité à des circuits fonctionnant sur cible reconfigurable. Le flot de conception présenté s’appuie sur un logiciel de synthèse de haut niveau et offre automatiquement la capacité de commutation aux circuits synthétisés. Les expériences menées sur un panel de circuits classiques montrent que l’ajout de cette capacité à un coût relativement faible ainsi qu’une rapidité de commutation sans égale dans la littérature

A Methodology for Invasive Programming on Virtualizable Embedded MPSoC Architectures

AbstractExploiting the huge logic resources in current embedded devices has led to a plethora of on-chip multi-processor architec- tures. However, besides instantiating more and more soft-core processors on a chip, developing applications suited for such architectures still remains a hard task. A further step in the evolution of embedded multi-processing might be the so called Invasive Programming. In this paradigm, an application may be switched from sequential to parallel execution at runtime. A task may then dynamically invade currently unused processor resources in a multi-processor system to resume in parallel execution mode. This hardens existing problems, however, because not only the development of suited software, but also the creation of multi-processor architectures supporting this paradigm is needed. Therefore, this work presents a concise methodology to enable Invasive Programming properties on an embedded Multi-Processor System-on-Chip (MPSoC). This is achieved by combining a designer-guided code parallelization approach with a virtualizable, generic, and scalable embedded MPSoC architecture. To resolve data dependencies during task invasion, a processor-independent task-based communication scheme for the MPSoC is proposed. Moreover, a tool framework dedicated to the generic creation of virtualizable MPSoC is provided. The approach is demonstrated by the generation of an MPSoC featuring eight processors executing an application which dynamically switches at runtime between sequential and parallel execution

A New Methodology to Manage FPGA Distributed Memory Content via Bitstream for Xilinx ZYNQ Devices

This paper proposes a methodology to access data and manage the content of distributed memories in FPGA designs through the configuration bitstream. Thanks to the methods proposed, it is possible to read and write the data content of registers without using the in/out ports of registers in a straightforward fashion. Hence, it offers the possibility of performing several operations, such as, to load, copy or compare the information stored in registers without the necessity of physical interconnections. This work includes two flows that simplify the designing process when using the proposed approach: while the first enables the protection or unprotection of writing on different partial regions through the bitstream, the second permits homogeneous instances of a design implemented in different reconfigurable regions to be obtained without losing efficiency. The approach is based and has been physically validated on the ZYNQ from Xilinx, and when using partially reconfigurable designs, it does not affect the hardware overhead nor the maximum operating frequency of the design.This work has been supported, within the fund for research groups of the Basque university system IT1440-22, by the Department of Education and, within PILAR ZE-2020/00022 and COMMUTE ZE-2021/00931 projects, by the Hazitek program, both of the Basque Government; the latter also by the Ministerio de Ciencia Innovación of Spain through the Centro para el Desarrollo Tecnológico Industrial (CDTI) within the projects IDI-20201264 and IDI-20220543, and through the Fondo Europeo de Desarrollo Regional 2014–2020 (FEDER funds)

A Memory Controller for FPGA Applications

As designers and researchers strive to achieve higher performance, field-programmable gate arrays (FPGAs) become an increasingly attractive solution. As coprocessors, FPGAs can provide application specific acceleration that cannot be matched by modern processors. Most of these applications will make use of large data sets, so achieving acceleration will require a capable interface to this data. The research in this thesis describes the design of a memory controller that is both efficient and flexible for FPGA applications requiring floating point operations. In particular, the benefits of certain design choices are explored, including: scalability, memory caching, and configurable precision. Results are given to prove the controller\u27s effectiveness and to compare various design trade-offs

Der ATLAS LVL2-Trigger mit FPGA-Prozessoren : Entwicklung, Aufbau und Funktionsnachweis des hybriden FPGA/CPU-basierten Prozessorsystems ATLANTIS

Diese Arbeit beschreibt die Konzeption und Realisierung des hybriden FPGA/CPU-basierten Prozessorsystems ATLANTIS als Triggerprozessor für das geplante ATLAS-Experiment am CERN. Auf der Basis von CompactPCI wird eine enge Verknüpfung zwischen einem Multi-FPGA-System und einer Standard-CPU umgesetzt. Das System ist in der Rechenleistung skalierbar und flexibel nutzbar. Dies wird durch die Aufteilung in spezifische FPGA-Boards für die Algorithmenausführung und I/O-Funktionalität und durch einen integrierten Privat-Bus erreicht. Die Untersuchungen mit dem ATLANTIS-System beziehen sich auf zwei Kernstellen der 2. Triggerstufe (LVL2). Zum einen soll die Ausführung zeitkritischer B-Physik-Triggeralgorithmen beschleunigt werden. Der im Rahmen dieser Arbeit als Funktionsnachweis durchgeführte Benchmark des Full-Scan-TRT-Algorithmus hat gezeigt, daß die Ausführung gegenüber einer Standard-CPU um einen Faktor 5.6 beschleunigt werden kann. Als zweite ATLAS-Anwendung werden mit dem ATLANTIS-System Studien zu den Readout-Systemen durchgeführt. Für Untersuchungen im LVL2-Prototypensystem ist eine dauerhafte Installation des ATLANTIS-Systems am CERN vorgesehen. Der universelle Charakter von ATLANTIS zeigt sich in weiteren Anwendungen, die für das System entwickelt werden und deren Umsetzung im Rahmen dieser Arbeit unterstützt wurde: Das sind Triggeraufgaben bei Experimenten an der GSI/Darmstadt, die beschleunigte Ausführung von 2D/3D-Bildverarbeitungsanwendungen und die Simulation von N-Körper-Systemen in der Astrophysik. Die Anwendungsentwicklung kann mit der standardisierten Hardwarebeschreibungssprache VHDL durchgeführt werden. Alternativ dazu kann die in Mannheim entwickelte Sprache CHDL benutzt werden. Die Entwicklungs-Tools werden durch das ATLANTIS-Betriebssystem ergänzt