Efficient Hybrid Continuous-Time/Discrete-Time Cascade Modulators for Wideband Applications

This paper analyses the use of hybrid continuous-time/discrete-time cascade ΣΔ modulators for the implementation of power-efficient analog-to-digital converters in broadband wireless communication systems. Two alternative implementations of multi-rate cascade architectures are studied and compared with conventional single-rate continuous-time topologies, taking into account the impact of main circuit-level error mechanisms, namely: mismatch, finite dc gain and gain-bandwidth product. In all cases, closed-form design equations are derived for the nonideal in-band noise power of all ΣΔ modulators under study, providing analytical relationships between their system-level performance and the corresponding circuit-level error parameters. Theoretical predictions match simulation results, showing that the lowest performance degradation is obtained by a new kind of multi-rate hybrid ΣΔ modulator, in which the front-end (continuous-time) stage operates at a higher rate than the back-end (discrete-time) stages. As a case study, the design of a hybrid GmC/switched-capacitor fourth-order (two-stage, 4-bit) cascade ΣΔ modulator is discussed to illustrate the potential benefits of the presented approachMinisterio de Economía y Competitividad TEC2010-14825/MI

Architectural Solutions for Analog Imperfections in ΔΣ Analog-to-Digital Based Systems

For today’s ubiquitous portable devices, innovative integrated circuits with high performance yet very low power are necessary. As these devices are used to communicate and sense real world signals in the environment, analog-to-digital converters (ADC) and systems are the key interface circuits needed to digitize the sensed information and they represent one of the most challenging aspects in the overall design. Fundamentally, this is due to the inherent imperfections in integrated circuit process technology because they cause degradations in the ADC performance. In this thesis, noise-shaping techniques are used to mitigate analog inaccuracies such as non-linearity and mismatch. These approaches are applied to ΔΣ analog-to-digital based systems. Two systems are presented in this work. The first is an architectural technique to highlight the benefits of low power, highly digital VCO-based analog-to-digital converters. It overcomes the limited SFDR due to VCO non-linearity. In this approach, a multi-loop delta-sigma (ΔΣ) ADC architecture is introduced that has a multi-rated VCO-based ADC in its second stage. A custom IC prototype of this architecture fabricated in a 130nm 1P8M CMOS process achieves 77.3dB signal-to-noise-ratio (SNR) over a 4MHz signal bandwidth with a power consumption of 13.8mW. The second system includes a new dynamic element matching (DEM) algorithm in the reference generating circuit of a ΔΣ modulator. The most basic DEM algorithm known as data weighted averaging (DWA) increases in-band noise due to intermodulation between the DEM tone and quantization error. In the proposed technique, by completing an integer multiple of the DEM cycles within one ΣΔ cycle, the DEM tone is moved to an integer multiple of the ΣΔ sample rate. As a result, with no additional circuitry or power consumption, the new DEM technique prevents any increase in the in-band noise. To prove its effectiveness, the DEM algorithm is embedded in a temperature-to-digital Converter (TDC) which requires a high precision reference. This TDC consists of a BJT-based temperature sensor followed by a 2nd-order feed-forward ΔΣ ADC as a readout circuit. It is fabricated in an 180nm 1P5M CMOS process consuming 5µA current from 1.4V supply voltage achieving resolution of 25mK/Conversion

A PROPOSAL OF LOW POWER MULTIPLE STATE ADC FOR ULTRASONIC DETECTION AND AUDIO BAND SIGNAL PROCESSING

In recent years, the function of laptop and smart phones have been improving and increasing. In this study, I focused on human detection using ultrasonic waves with MEMS microphones. Therefore, I proposed a multiple state ADC that takes the appropriate mode for an audio band and ultrasonic band processing. When switching between the two modes, the number of active transistors is switched to reduce the current consumption. In addition, the circuit configuration is also changed by switching. As a result, SNR of 99.7dB for audio signal processing and low current consumption of 187uA for ultrasonic detection was achieved

Design of sigma-delta modulators for analog-to-digital conversion intensively using passive circuits

This thesis presents the analysis, design implementation and experimental evaluation of passiveactive discrete-time and continuous-time Sigma-Delta (ΣΔ) modulators (ΣΔMs) analog-todigital converters (ADCs). Two prototype circuits were manufactured. The first one, a discrete-time 2nd-order ΣΔM, was designed in a 130 nm CMOS technology. This prototype confirmed the validity of the ultra incomplete settling (UIS) concept used for implementing the passive integrators. This circuit, clocked at 100 MHz and consuming 298 μW, achieves DR/SNR/SNDR of 78.2/73.9/72.8 dB, respectively, for a signal bandwidth of 300 kHz. This results in a Walden FoMW of 139.3 fJ/conv.-step and Schreier FoMS of 168 dB. The final prototype circuit is a highly area and power efficient ΣΔM using a combination of a cascaded topology, a continuous-time RC loop filter and switched-capacitor feedback paths. The modulator requires only two low gain stages that are based on differential pairs. A systematic design methodology based on genetic algorithm, was used, which allowed decreasing the circuit’s sensitivity to the circuit components’ variations. This continuous-time, 2-1 MASH ΣΔM has been designed in a 65 nm CMOS technology and it occupies an area of just 0.027 mm2. Measurement results show that this modulator achieves a peak SNR/SNDR of 76/72.2 dB and DR of 77dB for an input signal bandwidth of 10 MHz, while dissipating 1.57 mW from a 1 V power supply voltage. The ΣΔM achieves a Walden FoMW of 23.6 fJ/level and a Schreier FoMS of 175 dB. The innovations proposed in this circuit result, both, in the reduction of the power consumption and of the chip size. To the best of the author’s knowledge the circuit achieves the lowest Walden FOMW for ΣΔMs operating at signal bandwidth from 5 MHz to 50 MHz reported to date

Structure-Preserving Model Reduction of Physical Network Systems

This paper considers physical network systems where the energy storage is naturally associated to the nodes of the graph, while the edges of the graph correspond to static couplings. The first sections deal with the linear case, covering examples such as mass-damper and hydraulic systems, which have a structure that is similar to symmetric consensus dynamics. The last section is concerned with a specific class of nonlinear physical network systems; namely detailed-balanced chemical reaction networks governed by mass action kinetics. In both cases, linear and nonlinear, the structure of the dynamics is similar, and is based on a weighted Laplacian matrix, together with an energy function capturing the energy storage at the nodes. We discuss two methods for structure-preserving model reduction. The first one is clustering; aggregating the nodes of the underlying graph to obtain a reduced graph. The second approach is based on neglecting the energy storage at some of the nodes, and subsequently eliminating those nodes (called Kron reduction).</p

Applications in Electronics Pervading Industry, Environment and Society

This book features the manuscripts accepted for the Special Issue “Applications in Electronics Pervading Industry, Environment and Society—Sensing Systems and Pervasive Intelligence” of the MDPI journal Sensors. Most of the papers come from a selection of the best papers of the 2019 edition of the “Applications in Electronics Pervading Industry, Environment and Society” (APPLEPIES) Conference, which was held in November 2019. All these papers have been significantly enhanced with novel experimental results. The papers give an overview of the trends in research and development activities concerning the pervasive application of electronics in industry, the environment, and society. The focus of these papers is on cyber physical systems (CPS), with research proposals for new sensor acquisition and ADC (analog to digital converter) methods, high-speed communication systems, cybersecurity, big data management, and data processing including emerging machine learning techniques. Physical implementation aspects are discussed as well as the trade-off found between functional performance and hardware/system costs