2,108 research outputs found
Digital Circuit Design Using Floating Gate Transistors
Floating gate (flash) transistors are used exclusively for memory applications today. These applications include SD cards of various form factors, USB flash drives and SSDs. In this thesis, we explore the use of flash transistors to implement digital logic circuits. Since the threshold voltage of flash transistors can be modified at a fine granularity during programming, several advantages are obtained by our flash-based digital circuit design approach. For one, speed binning at the factory can be controlled with precision. Secondly, an IC can be re-programmed in the field, to negate effects such as aging, which has been a significant problem in recent times, particularly for mission-critical applications. Thirdly, unlike a regular MOSFET, which has one threshold voltage level, a flash transistor can have multiple threshold voltage levels. The benefit of having multiple threshold voltage levels in a flash transistor is that it allows the ability to encode more symbols in each device, unlike a regular MOSFET. This allows us to implement multi-valued logic functions natively. In this thesis, we evaluate different flash-based digital circuit design approaches and compare their performance with a traditional CMOS standard cell-based design approach. We begin by evaluating our design approach at the cell level to optimize the designās delay, power energy and physical area characteristics. The flash-based approach is demonstrated to be better than the CMOS standard cell approach, for these performance metrics. Afterwards, we present the performance of our design approach at the block level. We describe a synthesis flow to decompose a circuit block into a network of interconnected flash-based circuit cells. We also describe techniques to optimize the resulting network of flash-based circuit cells using donāt cares. Our optimization approach distinguishes itself from other optimization techniques that use donāt cares, since it a) targets a flash-based design flow, b) optimizes clusters of logic nodes at once instead of one node at a time, c) attempts to reduce the number of cubes instead of reducing the number of literals in each cube and d) performs optimization on the post-technology mapped netlist which results in a direct improvement in result quality, as compared to pre-technology mapping logic optimization that is typically done in the literature. The resulting network characteristics (delay, power, energy and physical area) are presented. These results are compared with a standard cell-based realization of the same block (obtained using commercial tools) and we demonstrate significant improvements in all the design metrics. We also study flash-based FPGA designs (both static and dynamic), and present the tradeoff of delay, power dissipation and energy consumption of the various designs. Our work differs from previously proposed flash-based FPGAs, since we embed the flash transistors (which store the configuration bits) directly within the logic and interconnect fabrics. We also present a detailed description of how the programming of the configuration bits is accomplished, for all the proposed designs
Digital Circuit Design Using Floating Gate Transistors
Floating gate (flash) transistors are used exclusively for memory applications today. These applications include SD cards of various form factors, USB flash drives and SSDs. In this thesis, we explore the use of flash transistors to implement digital logic circuits. Since the threshold voltage of flash transistors can be modified at a fine granularity during programming, several advantages are obtained by our flash-based digital circuit design approach. For one, speed binning at the factory can be controlled with precision. Secondly, an IC can be re-programmed in the field, to negate effects such as aging, which has been a significant problem in recent times, particularly for mission-critical applications. Thirdly, unlike a regular MOSFET, which has one threshold voltage level, a flash transistor can have multiple threshold voltage levels. The benefit of having multiple threshold voltage levels in a flash transistor is that it allows the ability to encode more symbols in each device, unlike a regular MOSFET. This allows us to implement multi-valued logic functions natively. In this thesis, we evaluate different flash-based digital circuit design approaches and compare their performance with a traditional CMOS standard cell-based design approach. We begin by evaluating our design approach at the cell level to optimize the designās delay, power energy and physical area characteristics. The flash-based approach is demonstrated to be better than the CMOS standard cell approach, for these performance metrics. Afterwards, we present the performance of our design approach at the block level. We describe a synthesis flow to decompose a circuit block into a network of interconnected flash-based circuit cells. We also describe techniques to optimize the resulting network of flash-based circuit cells using donāt cares. Our optimization approach distinguishes itself from other optimization techniques that use donāt cares, since it a) targets a flash-based design flow, b) optimizes clusters of logic nodes at once instead of one node at a time, c) attempts to reduce the number of cubes instead of reducing the number of literals in each cube and d) performs optimization on the post-technology mapped netlist which results in a direct improvement in result quality, as compared to pre-technology mapping logic optimization that is typically done in the literature. The resulting network characteristics (delay, power, energy and physical area) are presented. These results are compared with a standard cell-based realization of the same block (obtained using commercial tools) and we demonstrate significant improvements in all the design metrics. We also study flash-based FPGA designs (both static and dynamic), and present the tradeoff of delay, power dissipation and energy consumption of the various designs. Our work differs from previously proposed flash-based FPGAs, since we embed the flash transistors (which store the configuration bits) directly within the logic and interconnect fabrics. We also present a detailed description of how the programming of the configuration bits is accomplished, for all the proposed designs
Cell Detection by Functional Inverse Diffusion and Non-negative Group SparsityPart II: Proximal Optimization and Performance Evaluation
In this two-part paper, we present a novel framework and methodology to
analyze data from certain image-based biochemical assays, e.g., ELISPOT and
Fluorospot assays. In this second part, we focus on our algorithmic
contributions. We provide an algorithm for functional inverse diffusion that
solves the variational problem we posed in Part I. As part of the derivation of
this algorithm, we present the proximal operator for the non-negative
group-sparsity regularizer, which is a novel result that is of interest in
itself, also in comparison to previous results on the proximal operator of a
sum of functions. We then present a discretized approximated implementation of
our algorithm and evaluate it both in terms of operational cell-detection
metrics and in terms of distributional optimal-transport metrics.Comment: published, 16 page
Overviews of Optimization Techniques for Geometric Estimation
We summarize techniques for optimal geometric estimation from noisy observations for computer
vision applications. We first discuss the interpretation of optimality and point out that geometric
estimation is different from the standard statistical estimation. We also describe our noise
modeling and a theoretical accuracy limit called the KCR lower bound. Then, we formulate estimation
techniques based on minimization of a given cost function: least squares (LS), maximum
likelihood (ML), which includes reprojection error minimization as a special case, and Sampson
error minimization. We describe bundle adjustment and the FNS scheme for numerically solving
them and the hyperaccurate correction that improves the accuracy of ML. Next, we formulate
estimation techniques not based on minimization of any cost function: iterative reweight, renormalization,
and hyper-renormalization. Finally, we show numerical examples to demonstrate that
hyper-renormalization has higher accuracy than ML, which has widely been regarded as the most
accurate method of all. We conclude that hyper-renormalization is robust to noise and currently is
the best method
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