Layout optimization in ultra deep submicron VLSI design

As fabrication technology keeps advancing, many deep submicron (DSM) effects have become increasingly evident and can no longer be ignored in Very Large Scale Integration (VLSI) design. In this dissertation, we study several deep submicron problems (eg. coupling capacitance, antenna effect and delay variation) and propose optimization techniques to mitigate these DSM effects in the place-and-route stage of VLSI physical design. The place-and-route stage of physical design can be further divided into several steps: (1) Placement, (2) Global routing, (3) Layer assignment, (4) Track assignment, and (5) Detailed routing. Among them, layer/track assignment assigns major trunks of wire segments to specific layers/tracks in order to guide the underlying detailed router. In this dissertation, we have proposed techniques to handle coupling capacitance at the layer/track assignment stage, antenna effect at the layer assignment, and delay variation at the ECO (Engineering Change Order) placement stage, respectively. More specifically, at layer assignment, we have proposed an improved probabilistic model to quickly estimate the amount of coupling capacitance for timing optimization. Antenna effects are also handled at layer assignment through a linear-time tree partitioning algorithm. At the track assignment stage, timing is further optimized using a graph based technique. In addition, we have proposed a novel gate splitting methodology to reduce delay variation in the ECO placement considering spatial correlations. Experimental results on benchmark circuits showed the effectiveness of our approaches

A Multiple-objective ILP based Global Routing Approach for VLSI ASIC Design

A VLSI chip can today contain hundreds of millions transistors and is expected to contain more than 1 billion transistors in the next decade. In order to handle this rapid growth in integration technology, the design procedure is therefore divided into a sequence of design steps. Circuit layout is the design step in which a physical realization of a circuit is obtained from its functional description. Global routing is one of the key subproblems of the circuit layout which involves finding an approximate path for the wires connecting the elements of the circuit without violating resource constraints. The global routing problem is NP-hard, therefore, heuristics capable of producing high quality routes with little computational effort are required as we move into the Deep Sub-Micron (DSM) regime. In this thesis, different approaches for global routing problem are first reviewed. The advantages and disadvantages of these approaches are also summarized. According to this literature review, several mathematical programming based global routing models are fully investigated. Quality of solution obtained by these models are then compared with traditional Maze routing technique. The experimental results show that the proposed model can optimize several global routing objectives simultaneously and effectively. Also, it is easy to incorporate new objectives into the proposed global routing model. To speedup the computation time of the proposed ILP based global router, several hierarchical methods are combined with the flat ILP based global routing approach. The experimental results indicate that the bottom-up global routing method can reduce the computation time effectively with a slight increase of maximum routing density. In addition to wire area, routability, and vias, performance and low power are also important goals in global routing, especially in deep submicron designs. Previous efforts that focused on power optimization for global routing are hindered by excessively long run times or the routing of a subset of the nets. Accordingly, a power efficient multi-pin global routing technique (PIRT) is proposed in this thesis. This integer linear programming based techniques strives to find a power efficient global routing solution. The results indicate that an average power savings as high as 32\% for the 130-nm technology can be achieved with no impact on the maximum chip frequency

MULTILEVEL ROUTING WITH ANTENNA AVOIDANCE 防止天線效應之多階繞線器

隨著製程技術進步到奈米境界，天線效應已對繞線問 題上造成很大的影響。天線效應是指導體上充電累積對閘 極造成退化的現象。特別在使用高密度離子的深次微米技 術下，天線效應會直接影響電路的可製造度及良率。除此 之外，持續增長的電路繞線複雜度也對既存的繞線演算法 造成極大的影響。在這篇論文裡，我們提出了一使用自建 跳線機制來防止繞線天線問題之創新多階繞線架構。實驗 結果指出，我們的方法可順利防止所有閘極上所產生的天 線效應問題

mSIGMA: A Multilevel Full-Chip Routing System Considering SIGnal-integrity and MAnufacturability

由於超大型積體電路技術的快速發展，晶片設計已經到達奈米製程的時代。但在奈米晶片實體設計中，繞線(routing)所造成的問題佔整體晶片設計效能的比例卻逐漸增加且面臨到許多問題，尤其是(1)設計複雜度、(2)訊號完整度(signal-integrity)及(3)製造度(manufacturability)等三大問題急需去處理。因此，本篇論文提出了一創新的多階層繞線器(mSIGMA)來解決訊號完整度及可製造度等問題。 早期的繞線問題是使用直接兩階段繞線方式(flat routing)，也就是全域繞線(global routing)及區域繞線(detailed routing)來處理繞線問題，但此解法受限在其對於處理大量資料時的延伸性，為了解決這問題，學者們提出了階層繞線(hierarchical routing)來解決較大量的繞線問題，其使用了分而治之(divide and conquer)的方式來降低問題複雜度，但階層繞線仍受限於其無法保留各切割區塊間的全域資訊，得到更精確的結果，為了解決此問題，學者提出了多階層繞線器來解決以上架構所產生的問題。 多階層架構包含兩個主要步驟：粗糙化(coarsening)及反粗糙化(uncoarsening)。與之前多階層繞線器架構不同的地方是，我們在粗糙化及反粗糙化之間，提出了一軌道指派(track assignment)階段來加快繞線速度及實作最佳化。除了此創新的多階層架構，我們也對串音問題(crosstalk)、效能問題(performance)、天線效應問題(antenna effect)甚至最近提出的X架構(X-architecture)做了深入的研究。實驗結果證明，我們的創新架構比其他方法具有較好的彈性來處理以上的問題。跟之前發表在電子設計自動化重要會議發表的多階層繞線器相比，我們的方法在串音、效能、天線效應及總線長上，都有明顯的改善。在X架構的研究上，跟我們實作在曼哈頓架構(Manhattan architecture)的多階層繞線器相比，在總線長及效能上也都得到了不錯的成果。As technology advances into nanometer territory, the paradigm shift of the routing problem is indispensable to cope with three major challenges: design complexity, signal-integrity problem, and manufacturability problem. As Moore's Law continues unencumbered into the nanometer era, chips are reaching 100 M gates in size, process geometries have shrunk to 90 nm and below, and engineers have to face compounded design complexity with every new design. These nanometer-scale designs require a new generation of physics-aware and manufacturing- aware routing. At 90 nm and below, there are so many signal-integrity issues that design teams cannot manually correct them all. Nanometer routers must prevent and correct these effects on-the-fly in order to reach timing closure. From a manufacturability standpoint, nanometer routers must explicitly support the ever increasing design complexity, and be capable of adapting to the requirements of timing, signal integrity, process antenna effect, and new interconnect architecture such as X-architecture. In this Dissertation, we propose a novel multilevel full-chip router, namely mSIGMA for SIGnal-integrity and MAnufacturability optimization. To handle the ever increasing design complexity of gigascale integration, the mSIGMA use a multilevel framework that has attracted much attention in the literature recently. The traditional multilevel framework employs a two-stage technique: coarsening followed by uncoarsening. The coarsening stage iteratively groups a set of circuit components (e.g., circuit nodes, cells, modules, routing tiles, etc.) based on a predefined cost metric until the number of components being considered is smaller than a threshold. Then, the uncoarsening stage iteratively ungroups a set of previously clustered circuit components and refines the solution by using optimization techniques. Different with the previous multilevel routing framework, we introduce an intermediate track assignment phase between coarsening and uncoarsening stages, to improve run-time and achieve optimization. To handle the signal-integrity problem, especially the crosstalk problem, we propose a fast layer/track assignment heuristic for crosstalk optimization. We first build the horizontal constraint graph (HCG) for all segments in the panel. For the crosstalk-driven layer assignment problem, we resort to a simple yet efficient heuristic by constructing a maximum spanning tree from the given HCG. Since a tree can be k colored in linear time if we have k layers, we shall first partition the vertices incident on edges with larger costs (coupling lengths) and allocates the corresponding segments to different layers. Then, our track assignment algorithm starts by finding the maximal sets of conflicting segments, and assigns these conflicting segments by the bipartite assignment graph till they are assigned in the panel. To handle the manufacturability problem, such as process antenna effect and the X-architecture, we also propose a desirable track assignment in our multilevel routing framework for manufacturability optimization. To solve the antenna effect, we propose a built-in jumper insertion approach for antenna effect avoidance. To take the advantage of the X-architecture, we also adopt our new multilevel routing framework for the X-based architecture, and the experimental results show the promise of wirelength and delay reduction.ABSTRACT i TABLE OF CONTENTS iii LIST OF FIGURES vii LIST OF TABLES xi CHAPTER 1 INTRODUCTION 1 1.1 Down to the Wire 1 1.2 Routing Requirements for the Nanometer Era 3 1.2.1 Signal-Integrity Problems 4 1.2.2 Manufacturability Problems 8 1.3 Overview of the Dissertation 11 1.3.1 Multilevel Routing Framework 11 1.3.2 Multilevel Full-Chip Routing Considering Crosstalk and Performance 12 1.3.3 Multilevel Full-Chip Routing Considering Antenna Effect Avoidance 13 1.3.4 Multilevel Full-Chip Routing for the X-Based Architecture 13 1.4 Organization of the Dissertation 14 CHAPTER 2 MULTILEVEL ROUTING FRAMEWORK 15 2.1 Traditional Routing 15 2.1.1 Sequential Approaches 16 2.1.2 Concurrent Approaches 17 2.1.3 Hierarchical Approaches 19 2.2 Multilevel Routing 21 2.2.1 Previous Multilevel Routing Framework 22 2.2.2 Our Multilevel Routing Framework 26 2.2.3 Routing Model 28 2.2.4 Multilevel Routing Model 29 CHAPTER 3 MULTILEVEL FULL-CHIP ROUTING CONSIDERING CROSSTALK AND PERFORMANCE 31 3.1 Introduction 31 3.2 Elmore Delay Model 34 3.3 Multilevel Routing Framework 36 3.3.1 Performance-Driven Routing Tree Construction 37 3.3.2 Crosstalk-Driven Layer/Track Assignment 45 3.4 Experimental Results 50 3.5 Summary 55 CHAPTER 4 MULTILEVEL FULL-CHIP ROUTING CONSIDERING ANTENNA EFFECT AVOIDANCE 57 4.1 Introduction 57 4.2 Antenna Effect Damage 60 4.3 Multilevel Routing Framework 64 4.3.1 Bottom-Up Optimal Jumper Prediction 66 4.3.2 Multilevel Routing with Antenna Avoidance 72 4.3 Experimental Results 76 4.3 Summary 77 CHAPTER 5 MULTILEVEL FULL-CHIP ROUTING FOR THE X-BASED ARCHI- TECTURE 79 5.1 Introduction 79 5.2 Multilevel X Routing Framework 83 5.3 X-Architecture Steiner Tree Construction 85 5.3.1 Three-Terminal Net Routing Based on X-Architecture 86 5.3.2 X-Steiner Tree Algorithm Based on Delaunay Triangulation 90 5.4 Routability-Driven Pattern Routing 91 5.5 Trapezoid-Shaped Track Assignment 93 5.6 Experimental Results 98 5.7 Summary 101 CHAPTER 6 CONCLUSION REMARKS AND FUTURE WORK 103 6.1 Multilevel Routing Framework 103 6.2 Multilevel Full-Chip Routing Framework Considering Crosstalk and Performance 104 6.3 Multilevel Full-Chip Routing Framework Considering Antenna Effect Avoidance 105 6.4 Multilevel Full-Chip Routing Framework for the X-Based Architecture 105 6.5 Future Work 106 BIBLIOGRAPHY 10