79 research outputs found
A Multiple-objective ILP based Global Routing Approach for VLSI ASIC Design
A VLSI chip can today contain hundreds of millions transistors and is expected to
contain more than 1 billion transistors in the next decade.
In order to handle this rapid growth in integration technology,
the design procedure is therefore divided into a sequence of design
steps. Circuit layout is the design step in which a physical
realization of a circuit is obtained from its functional description.
Global routing is one of the key subproblems of the circuit layout
which involves finding an approximate path for the wires connecting the
elements of the circuit without violating resource constraints.
The global routing problem is NP-hard, therefore, heuristics capable of
producing high quality routes with little computational effort are required
as we move into the Deep Sub-Micron (DSM) regime.
In this thesis, different approaches for global routing problem are first
reviewed. The advantages and disadvantages of these approaches are also summarized.
According to this literature review, several mathematical programming based global
routing models are fully investigated. Quality of solution obtained by
these models are then compared with traditional Maze routing technique.
The experimental results show that the proposed model can optimize several global routing
objectives simultaneously and effectively. Also, it is easy to incorporate new
objectives into the proposed global routing model.
To speedup the computation time of the proposed ILP based global router, several
hierarchical methods are combined with the flat ILP based global routing
approach. The experimental results indicate that the bottom-up global routing
method can reduce the computation time effectively with a slight increase of maximum
routing density.
In addition to wire area, routability, and vias, performance and low power
are also important goals in global routing, especially in deep submicron designs.
Previous efforts that focused on power optimization for global routing
are hindered by excessively long run times or the routing of a subset of the
nets. Accordingly, a power efficient multi-pin global routing
technique (PIRT) is proposed in this thesis.
This integer linear programming based techniques strives to find a power
efficient global routing solution.
The results indicate that an average power savings as high as 32\% for the
130-nm technology can be achieved with no impact on the maximum chip frequency
Optimal joint routing and link scheduling for real-time traffic in TDMA Wireless Mesh Networks
We investigate the problem of joint routing and link scheduling in Time-Division Multiple Access (TDMA) Wireless Mesh Networks (WMNs) carrying real-time traffic. We propose a framework that always computes a feasible solution (i.e. a set of paths and link activations) if there exists one, by optimally solving a mixed integer-non linear problem. Such solution can be computed in minutes or tens thereof for e.g. grids of up to 4x4 nodes. We also propose heuristics based on Lagrangian decomposition to compute suboptimal solutions considerably faster and/or for larger WMNs, up to about 50 nodes. We show that the heuristic solutions are near-optimal, and we exploit them to gain insight on the schedulability in WMN, i.e. to investigate the optimal placement of one or more gateways from a delay bound perspec-tive, and to investigate how the schedulability is affected by the transmission range
Shortest Paths and Steiner Trees in VLSI Routing
Routing is one of the major steps in very-large-scale integration (VLSI) design. Its task is to find disjoint wire connections between sets of points on a chip, subject to numerous constraints. This problem is solved in a two-stage approach, which consists of so-called global and detailed routing steps. For each set of metal components to be connected, global routing reduces the search space by computing corridors in which detailed routing sequentially determines the desired connections as shortest paths. In this thesis, we present new theoretical results on Steiner trees and shortest paths, the two main mathematical concepts in routing. In the practical part, we give computational results of BonnRoute, a VLSI routing tool developed at the Research Institute for Discrete Mathematics at the University of Bonn. Interconnect signal delays are becoming increasingly important in modern chip designs. Therefore, the length of paths or direct delay measures should be taken into account when constructing rectilinear Steiner trees. We consider the problem of finding a rectilinear Steiner minimum tree (RSMT) that --- as a secondary objective --- minimizes a signal delay related objective. Given a source we derive some structural properties of RSMTs for which the weighted sum of path lengths from the source to the other terminals is minimized. Also, we present an exact algorithm for constructing RSMTs with weighted sum of path lengths as secondary objective, and a heuristic for various secondary objectives. Computational results for industrial designs are presented. We further consider the problem of finding a shortest rectilinear Steiner tree in the plane in the presence of rectilinear obstacles. The Steiner tree is allowed to run over obstacles; however, if it intersects an obstacle, then no connected component of the induced subtree must be longer than a given fixed length. This kind of length restriction is motivated by its application in VLSI routing where a large Steiner tree requires the insertion of repeaters which must not be placed on top of obstacles. We show that there are optimal length-restricted Steiner trees with a special structure. In particular, we prove that a certain graph (called augmented Hanan grid) always contains an optimal solution. Based on this structural result, we give an approximation scheme for the special case that all obstacles are of rectangular shape or are represented by at most a constant number of edges. Turning to the shortest paths problem, we present a new generic framework for Dijkstra's algorithm for finding shortest paths in digraphs with non-negative integral edge lengths. Instead of labeling individual vertices, we label subgraphs which partition the given graph. Much better running times can be achieved if the number of involved subgraphs is small compared to the order of the original graph and the shortest path problems restricted to these subgraphs is computationally easy. As an application we consider the VLSI routing problem, where we need to find millions of shortest paths in partial grid graphs with billions of vertices. Here, the algorithm can be applied twice, once in a coarse abstraction (where the labeled subgraphs are rectangles), and once in a detailed model (where the labeled subgraphs are intervals). Using the result of the first algorithm to speed up the second one via goal-oriented techniques leads to considerably reduced running time. We illustrate this with the routing program BonnRoute on leading-edge industrial chips. Finally, we present computational results of BonnRoute obtained on real-world VLSI chips. BonnRoute fulfills all requirements of modern VLSI routing and has been used by IBM and its customers over many years to produce more than one thousand different chips. To demonstrate the strength of BonnRoute as a state-of-the-art industrial routing tool, we show that it performs excellently on all traditional quality measures such as wire length and number of vias, but also on further criteria of equal importance in the every-day work of the designer
Optimal joint routing and link scheduling for real-time traffic in TDMA Wireless Mesh Networks
We investigate the problem of joint routing and link scheduling in Time-Division Multiple Access (TDMA) Wireless Mesh Networks (WMNs) carrying real-time traffic. We propose a framework that always computes a feasible solution (i.e. a set of paths and link activations) if there exists one, by optimally solving a mixed integer-non linear problem. Such solution can be computed in minutes or tens thereof for e.g. grids of up to 4x4 nodes. We also propose heuristics based on Lagrangian decomposition to compute suboptimal solutions considerably faster and/or for larger WMNs, up to about 50 nodes. We show that the heuristic solutions are near-optimal, and we exploit them to investigate the optimal placement of one or more gateways from a delay bound perspective
Recommended from our members
Synthesis of On-Chip Interconnection Structures:From Point-to-Point Links to Networks-on-Chip
Packet-switched networks-on-chip (NOC) have been advocated as the solution to the challenge of organizing efficient and reliable communication structures among the components of a system-on-chip (SOC). A critical issue in designing a NOC is to determine its topology given the set of point-to-point communication requirements among these components. We present a novel approach to on-chip communication synthesis that is based on the iterative combination of two efficient computational steps: (1) an application of the k-Median algorithm to coarsely determine the global communication structure (which may turned out not be a network after all), and a (2) a variation of the shortest-path algorithm in order to finely tune the data flows on the communication channels. The application of our method to case studies taken from the literature shows that we can automatically synthesize optimal NOC topologies for multi-core on-chip processors and it offers new insights on why NOC are not necessarily a value proposition for some classes of applcation-specific SOCs
Segment Routing: a Comprehensive Survey of Research Activities, Standardization Efforts and Implementation Results
Fixed and mobile telecom operators, enterprise network operators and cloud
providers strive to face the challenging demands coming from the evolution of
IP networks (e.g. huge bandwidth requirements, integration of billions of
devices and millions of services in the cloud). Proposed in the early 2010s,
Segment Routing (SR) architecture helps face these challenging demands, and it
is currently being adopted and deployed. SR architecture is based on the
concept of source routing and has interesting scalability properties, as it
dramatically reduces the amount of state information to be configured in the
core nodes to support complex services. SR architecture was first implemented
with the MPLS dataplane and then, quite recently, with the IPv6 dataplane
(SRv6). IPv6 SR architecture (SRv6) has been extended from the simple steering
of packets across nodes to a general network programming approach, making it
very suitable for use cases such as Service Function Chaining and Network
Function Virtualization. In this paper we present a tutorial and a
comprehensive survey on SR technology, analyzing standardization efforts,
patents, research activities and implementation results. We start with an
introduction on the motivations for Segment Routing and an overview of its
evolution and standardization. Then, we provide a tutorial on Segment Routing
technology, with a focus on the novel SRv6 solution. We discuss the
standardization efforts and the patents providing details on the most important
documents and mentioning other ongoing activities. We then thoroughly analyze
research activities according to a taxonomy. We have identified 8 main
categories during our analysis of the current state of play: Monitoring,
Traffic Engineering, Failure Recovery, Centrally Controlled Architectures, Path
Encoding, Network Programming, Performance Evaluation and Miscellaneous...Comment: SUBMITTED TO IEEE COMMUNICATIONS SURVEYS & TUTORIAL
Diastolic arrays : throughput-driven reconfigurable computing
Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2008.Includes bibliographical references (leaves 67-70).In this thesis, we propose a new reconfigurable computer substrate: diastolic arrays. Diastolic arrays are arrays of processing elements that communicate exclusively through First-In First-Out (FIFO) queues, and provide hardware support to guarantee bandwidth and buffer space for all data transfers. FIFO control implies that a module idles if its input FIFOs are empty, and stalls if its output FIFOs are full. The timing of data transfers between processing elements in diastolic arrays is therefore significantly more relaxed than in systolic arrays or pipelines. All specified data transfers are statically routed, and the routing problem to maximize average throughput can be optimally or near-optimally solved in polynomial time by formulating it as a maximum concurrent multicommodity flow problem and using linear programming. We show that the architecture of diastolic arrays enables efficient synthesis from high-level specifications of communicating finite state machines, providing a high-performance, off-the-shelf computer substrate that can be easily programmed.by Myong Hyon Cho.S.M
Scheduled routing for the NuMesh
Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1994.Includes bibliographical references (leaves 66-68).by Milan Singh Minsky.M.S
- …