Physics-Based Electromigration Modeling and Analysis and Optimization

Long-term reliability is a major concern in modern VLSI design. Literature has shown that reliability gets worse as technology advances. It is expected that the future VLSI systems would have shorter reliability-induced lifetime comparing with previous generations. Being one of the most serious reliability effects, electromigration (EM) is a physical phenomenon of the migration of metal atoms due to the momentum exchange between atoms and the conducting electrons. It can cause wire resistance change or open circuit and result in functional failure of the circuit. Power-ground networks are the most vulnerable part to EM effect among all the interconnect wires since the current flow on this part is the largest on the chip. With new generation oftechnology node and aggressive design strategies, more accurate and efficient EM models are required. However, traditional EM approaches are very conservative and cannot meet current aggressive design strategies. Besides circuit level, EM also need to be thoroughly studied in system level due to limited power and temperature budgets among cores on chip. This research focuses on developing physical level EM model for VLSI circuits and system level EM optimization for multi-core systems in order to overcome the aforementioned problems. Specifically, for physical level, we develop two EM immortality check methods and a power grid EM check method. Firstly, a voltage based EM immortality analysis has been developed. Immortality condition in nucleation phase can be determined fast and accurately for multi-segment interconnect wires. Secondly, a saturation volume based incubation phase immortality check method has been proposed. This method can further reduce the redundancy in VLSI circuit design by immortality check in multiphase. Furthermore, both immortality check methods are integrated into a new power grid EM check methodology (EMspice) as filter for EM analysis. These filters can accelerate the simulation by filtering out immortal trees so that we only need to do simulation on fewer trees that are mortal. Coupled EM simulation considering both hydrostatic stress and electronic current/voltage in the power grid network will be applied to these mortal trees. This tool can work seamlessly with commercial synthesis flow. Besides physical level reliability models, system level reliability optimization is also discussed in this research. A deep reinforcement learning based EM optimization has been proposed for multi-core system. Both long term reliability effect (hard error) and transient soft error are considered. Energy can be optimized with all the reliability and other constraints fast and accurately compared to existing reliability management techniques. Last but not least, a scheduling based reliability optimization method for multi-core systems has been proposed. NBTI, HCI and EM are considered jointly. Lifetime of the system can be improved significantly compared to traditional methods which mainly focus on utilization

Scaling and process effect on electromigration reliability for Cu/low k interconnects

textThe microelectronics industry has been managing the RC delay problem arising from aggressive line scaling, by replacing aluminum (Al) by copper (Cu) and oxide dielectric by low-k dielectric. Electromigration (EM) turned out to be a serious reliability problem for Cu interconnects due to the implementation of mechanically weaker low-k dielectrics. In addition, line width and via size scaling resulted in the need of a novel diffusion barrier, which should be uniform and thin. The objective of this dissertation is to investigate the impacts of Ta barrier process, such as barrier-first and pre-clean first, and scaling of barrier and line/via on EM reliability of Cu/low-k interconnects. For this purpose, EM statistical test structures, having different number of line segments, line width, and via width, were designed. The EM test structures were fabricated by a dualdamascene process with two metal layers (M1/Via/M2), which were then packaged for EM tests. The package-level EM tests were performed in a specially designed vacuum chamber with pure nitrogen environment. The novel barrier deposition process, called barrier-first, showed a higher (jL)[subscript c] product and prolonged EM lifetime, compared with the conventional Ta barrier deposition process, known as pre-clean first. This can be attributed to the improved uniformity and thickness of the Ta layer on the via and trench, as confirmed by TEM. As for the barrier thickness effect, the (jL)c product decreased with decreasing thickness, due to reduced Cu confinement. A direct correlation between via size and EM reliability was found; namely, EM lifetime and statistics degraded with via size. This can be attributed to the fact that critical void length to cause open circuit is about the size of via width. To investigate further line scaling effect on EM reliability, SiON (siliconoxynitride) trenchfilling process was introduced to fabricate 60-nm lines, corresponding to 45-nm technology, using a conventional, wider line lithograph technology. The EM lifetime of 60-nm fine lines with SiON filling was longer than that of a standard damascene structure, which can be attributed to a distinct via/metal-1 configuration in reducing process-induced defects at the via/metal-1 interface.Materials Science and Engineerin

Accelerating Electromigration Aging: Fast Failure Detection for Nanometer ICs

For practical testing and detection of electromigration (EM) induced failures in dual damascene copper interconnects, one critical issue is creating stressing conditions to induce the chip to fail exclusively under EM in a very short period of time so that EM sign-off and validation can be carried out efficiently. Existing acceleration techniques, which rely on increasing temperature and current densities beyond the known limits, also accelerate other reliability effects making it very difficult, if not impossible, to test EM in isolation. In this article, we propose novel EM wear-out acceleration techniques to address the aforementioned issue. First we show that multi-segment interconnects with reservoir and sink structures can be exploited to significantly speedup the EM wear-out process. Based on this observation, we propose three strategies to accelerate EM induced failure: reservoir-enhanced acceleration, sink-enhanced acceleration, and a hybrid method that combines both reservoir and sink structures. We then propose several configurable interconnect structures that exploit atomic reservoirs and sinks for accelerated EM testing. Such configurable interconnect structures are very flexible and can be used to achieve significant lifetime reductions at the cost of some routing resources. Using the proposed technique, EM testing can be carried out at nominal current densities, and at a much lower temperature compared to traditional testing methods. This is the most significant contribution of this work since, to our knowledge, this is the only method that allows EM testing to be performed in a controlled environment without the risk of invoking other reliability effects that are also accelerated by elevated temperature and current density. Simulation results show that, using the proposed method, we can reduce the EM lifetime of a chip from 10 years down to a few hours 10^5X acceleration under the 150C temperature limit, which is sufficient for practical EM testing of typical nanometer CMOS ICs

Interconnect Aging—Physics to Software

Device reliability or lifetime is often non-negotiable and crucial for sensitive applications such as medical devices, autonomous vehicles and space crafts. Inevitable technology advancement (e.g. miniaturization) has added unwelcome complications and unpredictability to the aging problem. Reliability of VLSI chips is jeopardized by mass transport in metallic interconnects. Material migration is caused by electrical, mechanical and thermal phenomena, and, therefore, is a complicated process. While all aspects of material migration have been studied, a comprehensive investigation that can explain and include all those phenomena simultaneously remains unsolved. Inaccuracies in modeling and predicting aging processes in wires cause that chipmakers often overdesign interconnects. This is an undesirable and expensive approach in terms of time and cost. In modern technologies, the predicted lifetime, aging, and failure mechanisms in interconnect very often do not match the observed behaviors. Unrealistic models used in CAD tools are the main culprit of such incompatibilities. In general, two situations may occur: (1) in some cases, the models may wrongly scrutinize reliability in unfailing parts and consequently impose unnecessary design tightening and (2) in some other cases, the models may underestimate serious reliability problems causing unpredicted behaviors or catastrophic failures to occur. The existing models for reliability evaluation are usually pessimistic in case of interconnect voiding and optimistic when extrusions occur. Time-consuming and not converging reliability assessments, as well as undesired chip behaviors, are the common expensive outcome of such models.We revisit the underlying physics of aging processes in dual-damascene copper lines. We demonstrate, that the simplistic modeling is the cause of the incompatibility of the existing models. We study all three main aging processes: electromigration, thermo-migration, and stress migration and offer several comprehensive yet compact models for realistic assessment of interconnect aging. These models explain many observations that have been inexplicable for decades. Ultimately, a computer-aided design tool, RAIN, is developed based on the proposed models and is capable of assessing the reliability of industry standard complex multi-layer, multi-segment interconnect networks. This tool can be readily integrated into other verification signoffs phases such as performance, timing, and power analyses. RAIN takes as inputs: (1) interconnect design, (2) technology specifications, (3) initial stress and temperature, (4) IR drop and lifetime requirements. It analyzes and assesses reliability and delivery requirements of all nets, and provides a report on voltage limitations, thermal violations and expected lifetime. It is validated on a wide spectrum of experimental results performed on various industry benchmarks

Study of initial void formation and electron wind force for scaling effects on electromigration in Cu interconnects

textThe continuing scaling of integrated circuits beyond 22nm technology node poses increasing challenges to Electromigration (EM) reliability for Cu on-chip interconnects. First, the width of Cu lines in advanced technology nodes is less than the electron mean free path which is 39nm in Cu at room temperature. This is a new size regime where any new scaling effect on EM is of basic interest. And second, the reduced line width necessitates the development of new methods to analyze the EM characteristics. Such studies will require the development of well controlled processes to fabricate suitable test structures for EM study and model verification. This dissertation is to address these critical issues for EM in Cu interconnects. The dissertation first studies the initial void growth under EM, which is critical for measurement of the EM lifetime and statistics. A method based on analyzing the resistance traces obtained from EM tests of multi-link structures has been developed. The results indicated that there are three stages in the resistance traces where the rate of the initial void growth in Stage I is lower than that in Stage III after interconnect failure and they are linearly correlated. An analysis extending the Korhonen model has been formulated to account for the initial void formation. In this analysis, the stress evolution in the line during void growth under EM was analyzed in two regions and an analytic solution was deduced for the void growth rate. A Monte Carlo grain growth simulation based on the Potts model was performed to obtain grain structures for void growth analysis. The results from this analysis agreed reasonably well with the EM experiments. The next part of the dissertation is to study the size effect on the electron wind force for a thin film and for a line with a rectangular cross section. The electron wind force was modeled by considering the momentum transfer during collision between electrons and an atom. The scaling effect on the electron wind force was found to be represented by a size factor depending on the film/line dimensions. In general, the electron wind force is enhanced with increasing dimensional confinement. Finally, a process for fabrication of Si nanotrenches was developed for deposition of Cu nanolines with well-defined profiles. A self-aligned sub-lithographic mask technique was developed using polymer residues formed on Si surfaces during reactive ion etching of Si dioxide in a fluorocarbon plasma. This method was capable to fabricate ultra-narrow Si nanotrenches down to 20nm range with rectangular profiles and smooth sidewalls, which are ideal for studying EM damage mechanisms and model verification for future technology nodes.Physic

Effects of mechanical properties on the reliability of Cu/low-k metallization systems

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Materials Science and Engineering, 2007.This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.Includes bibliographical references (leaves 211-217).Cu and low-dielectric-constant (k) metallization schemes are critical for improved performance of integrated circuits. However, low elastic moduli, a characteristic of the low-k materials, lead to significant reliability degradation in Cu-interconnects. A thorough understanding of the effects of mechanical properties on electromigration induced failures is required for accurate reliability assessments. During electromigration inside Cu-interconnects, a change in atomic concentration correlates with a change in stress through the effective bulk modulus of the materials system, B, which decreases as the moduli of low-k materials used as inter-level dielectrics (ILDs) decrease. This property is at the core of discussions on electromigration-induced failures by all mechanisms. B is computed using finite element modeling analyses, using experimentally determined mechanical properties of the individual constituents. Characterization techniques include nanoindentation, cantilever deflection, and pressurized membrane deflection for elastic properties measurements, and chevron-notched double-cantilever pull structures for adhesion measurements. The dominant diffusion path in Cu-interconnects is the interface between Cu and the capping layer, which is currently a Si3N4-based film. We performed experiments on Cu-interconnect segments to investigate the kinetics of electromigration. A steady resistance increase over time prior to open-circuit failure, a result of void growth, correlates with the electromigration drift velocity. Diffusive measurements made in this fashion are more fundamental than lifetime measurements alone, and correlate with the combined effects of the electron wind and the back stress forces during electromigration induced void growth.(cont.)Using this method, the electromigration activation energy was determined to be 0.80±0.06eV. We conducted experiments using Cu-interconnects with different lengths to study line length effects. Although a reliability improvement is observed as the segment length decreases, there is no deterministic current-density line-length product, jL, for which all segments are immortal. This is because small, slit-like voids forming directly below vias will cause open-failures in Cu-interconnects. Therefore, the probabilistic jLcrit values obtained from via-above type nterconnects approximate the thresholds for void nucleation. The fact that jLcrit,nuc monotonically decreases with B results from an energy balance between the strain energy released and surface energy cost for void nucleation and the critical stress required for void nucleation is proportional to B. We also performed electromigration experiments using Cu/low-k interconnect trees to investigate the effects of active atomic sinks and reservoirs on interconnect reliability. In all cases, failures were due to void growth. Kinetic parameters were extracted to be ... Quantitative analysis demonstrates that the reliability of the failing segments is modulated by the evolution of stress in the whole interconnect tree. During this process, not only the diffusive parameters but also B play critical roles. However, as B decreases, the positive effects of reservoirs on reliability are diminished, while the negative effects of sinks on reliability are amplified.(cont.) Through comprehensive failure analyses, we also successfully identified the mechanism of electromigration-induced extrusions in Cu/low-k interconnects to be nearmode-I interfacial fracture between the Si3N4-based capping layer and the metallization/ILD layer below. The critical stress required for extrusion is found to depend not only on B but also on the layout and dimensions of the interconnects. As B decreases, sparsely packed, wide interconnects are most prone to extrusion-induced failures. Altogether, this research accounts for the effects of mechanical properties on all mechanisms of failure due to electromigration. The results provide an improved experimental basis for accurate circuit-level, layout-specific reliability assessments.by Frank LiLi Wei.Ph.D

Characterization of Thermo-Mechanical Damage in Tin and Sintered Nano-Silver Solders

abstract: Increasing density of microelectronic packages, results in an increase in thermal and mechanical stresses within the various layers of the package. To accommodate the high-performance demands, the materials used in the electronic package would also require improvement. Specifically, the damage that often occurs in solders that function as die-attachment and thermal interfaces need to be addressed. This work evaluates and characterizes thermo-mechanical damage in two material systems – Electroplated Tin and Sintered Nano-Silver solder. Tin plated electrical contacts are prone to formation of single crystalline tin whiskers which can cause short circuiting. A mechanistic model of their formation, evolution and microstructural influence is still not fully understood. In this work, growth of mechanically induced tin whiskers/hillocks is studied using in situ Nano-indentation and Electron Backscatter Diffraction (EBSD). Electroplated tin was indented and monitored in vacuum to study growth of hillocks without the influence of atmosphere. Thermal aging was done to study the effect of intermetallic compounds. Grain orientation of the hillocks and the plastically deformed region surrounding the indent was studied using Focused Ion Beam (FIB) lift-out technique. In addition, micropillars were milled on the surface of electroplated Sn using FIB to evaluate the yield strength and its relation to Sn grain size. High operating temperature power electronics use wide band-gap semiconductor devices (Silicon Carbide/Gallium Nitride). The operating temperature of these devices can exceed 250oC, preventing use of traditional Sn-solders as Thermal Interface materials (TIM). At high temperature, the thermomechanical stresses can severely degrade the reliability and life of the device. In this light, new non-destructive approach is needed to understand the damage mechanism when subjected to reliability tests such as thermal cycling. In this work, sintered nano-Silver was identified as a promising high temperature TIM. Sintered nano-Silver samples were fabricated and their shear strength was evaluated. Thermal cycling tests were conducted and damage evolution was characterized using a lab scale 3D X-ray system to periodically assess changes in the microstructure such as cracks, voids, and porosity in the TIM layer. The evolution of microstructure and the effect of cycling temperature during thermal cycling are discussed.Dissertation/ThesisDoctoral Dissertation Materials Science and Engineering 201

Electric field-induced directed assembly of diblock copolymers and grain boundary grooving in metal interconnects

Das Anlegen eines elektrischen Feldes an Materialien hat eine faszinierende Wirkung. Unterschiedliche Werkstoffklassen sind einem externen elektrischen Feld entweder als ein Teil der Verarbeitung oder aufgrund der alleinigen Applikation ausgesetzt. Wenn das elektrische Feld für die Verarbeitung verwendet wird, kann dieses die Mikrostruktur in Metallen, Legierungen, Keramiken und Polymeren verändern, wodurch die physikalischen Eigenschaften verändert werden. Alternativ können mehrere Einsatzmöglichkeiten wie beispielsweise der Einsatz in elektronischen Geräten dazu führen, dass Materialien als Komponenten verwendet werden, die täglich intensiven Stromstärken ausgesetzt sind. Eine ständige Verlagerung der Atome kann zu Fehlern im offenen Stromkreis führen, wodurch die Zuverlässigkeit des gesamten Geräts beeinträchtigt wird. Mit Hilfe der Phasenfeldmethode wird in der vorliegenden Dissertation jeweils ein Anwendungsfall untersucht, in dem das elektrische Feld entweder positive oder negative Folgen haben kann. Im ersten Teil der Arbeit wird ein diffuses Grenzflächenmodell entwickelt und für die Untersuchung der gerichteten Selbstorganisation von symmetrischen Diblock-Copolymeren verwendet, die gleichzeitig durch das elektrische Feld, die Substrataffinität und die Beschränkung beeinflusst werden. Es werden verschiedene beschränkende Geometrien untersucht und eine Reihe an Phasendiagrammen für unterschiedliche Schichtdicken charakterisiert, die das Verhältnis zwischen dem elektrischen Feld und der Substratstärke zeigen. Zusätzlich zu der Ermittlung der vorhandenen parallelen, senkrechten und gemischten Lamellenphasen findet man, ähnlich wie bei den vorausgegangenen analytischen Berechnungen und experimentellen Beobachtungen, auch einen Bereich im Phasendiagramm, der einem Lamellenabstand der Größe eines halben Integrals entspricht, in dem hybride Morphologien wie Benetzungsschichten in der Nachbarschaft des Substrats koexistieren, die entweder Löcher in der Mitte der Schicht oder senkrechte zylinderförmige Bereiche aufweisen. Des Weiteren wird die Untersuchung auf drei Dimensionen erweitert, in denen die letztgenannte Morphologie als eine hexagonal perforierte (HPL) Lamellenphase charakterisiert wird. Erstmals wird gezeigt, dass durch ein elektrisches Feld ein Ordnungs-Ordnungs-übergang von einer Lamellenphase zu einer HPL-Phase hervorgerufen werden kann. Außerdem zeigt der kinetische Verlauf des Übergangs, dass es sich bei den perforierten Lamellen, die während des Übergangs von parallelen zu senkrechten Lamellen in Dünnschichten entstehen, um Zwischenstrukturen handelt. Im Folgenden werden verschiedene Beschädigungsarten erläutert, die aufgrund der Elektromigration (EM) in Nanoverbindungen durch die Rille der Korngrenze verursacht werden. Dazu wird ein einkomponentiges, polykristallines Phasenfeldmodell verwendet, das die Windstärke der Elektronen berücksichtigt. Das Modell und dessen numerische Umsetzung wird erst mit der scharfen Grenzflächentheorie von Mullins verglichen, bei der die thermische Rillenbildung durch Oberflächendiffusion vermittelt wird. Anschließend wird gezeigt, dass die Art der durch die fortschreitende Elektromigration verursachten Schädigung stark durch einen Fluss durch Grenzflächen beeinträchtigt werden kann, der aufgrund der Elektromigration stattfindet. Ein schneller atomarer Transport entlang der Oberfläche führt zu einer formerhaltenden Versetzung der Oberfläche, während der Schaden durch einen schnelleren atomaren Transport durch Grenzflächen in Form von interkristallinen Schlitzen mit einer formerhaltenden Spitze lokalisiert wird. Durch die Phasenfeldsimulationen wird die Funktion von krümmungs- und EM-induzierten heilenden Strömungen entlang der Oberfläche weiter hervorgehoben, die die Rille wieder auffüllen und die Schadensausbreitung verzögern. Erstmals wird ein numerisches Modell erweitert, um die räumlich-zeitliche Schadenseinleitung, die Ausbreitung, die Selbstheilung und die Kornvergröberung in dreidimensionalen Verbindungen zu untersuchen. Anschließend zeigt ein kritischer Vergleich der aus der scharfen Grenzflächenmethode und der Phasenfeldmethode gewonnenen Lösungen bezüglich der Rillenbildung, dass sowohl bei der Ermittlung der Rillenformen als auch beim Verlauf der Schadensart erhebliche Fehler entstehen können, wenn der durch die Elektromigration induzierte Oberflächenfluss in den Theorien der scharfen Grenzflächen nicht berücksichtigt wird. Zur Beseitigung der Diskrepanzen wird schließlich ein neues scharfes Grenzflächenmodell für finite Körner formuliert, das die zeitgleiche Kapillarwirkung und den durch die Elektromigration induzierten Oberflächen- und Grenzflächenfluss berücksichtigt. Die mit dem neuen Modell getroffenen Vorhersagen zeigen eine sehr gute Übereinstimmung mit dem Phasenfeldmodell. Durch die Ergebnisse der vorliegenden Arbeit wird die Durchführbarkeit und Anwendbarkeit der Phasenfeldmethode in Bezug auf die Erfassung der erforderlichen Physik des Problems und in Bezug auf die Bewältigung der mikrostrukturellen Entwicklung effizient und elegant in einem Phänomen verdeutlicht, das durch ein elektrisches Feld verursacht wird

All-copper chip-to-substrate interconnects for high performance integrated circuit devices

In this work, all-copper connections between silicon microchips and substrates are developed. The semiconductor industry advances the transistor density on a microchip based on the roadmap set by Moore's Law. Communicating with a microprocessor which has nearly one billion transistors is a daunting challenge. Interconnects from the chip to the system (i.e. memory, graphics, drives, power supply) are rapidly growing in number and becoming a serious concern. Specifically, the solder ball connections that are formed between the chip itself and the package are challenging to make and still have acceptable electrical and mechanical performance. These connections are being required to increase in number, increase in power current density, and increase in off-chip operating frequency. Many of the challenges with using solder connections are limiting these areas. In order to advance beyond the limitations of solder for electrical and mechanical performance, a novel approach to creating all-copper connections from the chip-to-substrate has been developed. The development included characterizing the electroless plating and annealing process used to create the connections, designing these connections to be compatible with the stress requirements for fragile low-k devices, and finally by improving the plating/annealing process to become process time competitive with solder. It was found that using a commercially available electroless copper bath for the plating, followed by annealing at 180 C for 1 hour, the shear strength of the copper-copper bond was approximately 165 MPa. This work resulted in many significant conclusions about the mechanism for bonding in the all-copper process and the significance of materials and geometry on the mechanical design for these connections.Ph.D.Committee Chair: Kohl, Paul; Committee Member: Bidstrup Allen, Sue Ann; Committee Member: Fuller, Thomas; Committee Member: Hesketh, Peter; Committee Member: Hess, Dennis; Committee Member: Meindl, Jame